AD7714YRUZ Analog Devices Inc, AD7714YRUZ Datasheet - Page 6

• Manufacturer Part Number: AD7714YRUZ
• Description: IC ADC SIGNAL COND 3/5V 24-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7714YRUZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 24
• Sampling Rate (per Second): 1k
• Number Of Converters: 1
• Power Dissipation (max): 7mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 24bit
• Sampling Rate: 1kSPS
• Input Channel Type: Differential
• Supply Voltage Range - Digital: 2.7V To 5.25V
• Supply Current: 1.1mA
• Number Of Elements: 1
• Resolution: 24Bit
• Architecture: Delta-Sigma
• Sample Rate: 1KSPS
• Input Polarity: Unipolar/Bipolar
• Input Type: Voltage
• Differential Input: Yes
• Power Supply Requirement: Analog and Digital
• Single Supply Voltage (typ): 3/5V
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.25V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 4.75mW
• Integral Nonlinearity Error: ±0.0015%FSR
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 24
• Package Type: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7714-3EBZ - BOARD EVALUATION FOR AD7714
• Lead Free Status / Rohs Status: Compliant

Parameter
LOGIC OUTPUTS (Continued))
TRANSDUCER BURNOUT
SYSTEM CALIBRATION
POWER REQUIREMENTS
NOTES
10
11
12
13
14
15
16
17
18
19
20
21
Specifications subject to change without notice.
AD7714Y
1
2
3
4
5
6
7
8
9
Temperature range is as follows: Y Version: –40 C to +105 C.
A calibration is effectively a conversion so these errors will be of the order of the conversion noise shown in Tables I to IV. This applies after calibration at the temperature of interest.
Recalibration at any temperature will remove these drift errors.
Positive Full-Scale Error includes Zero-Scale Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges.
Full-Scale Drift includes Zero-Scale Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges.
Gain Error does not include Zero-Scale Errors. It is calculated as Full-Scale Error—Unipolar Offset Error for unipolar ranges and Full-Scale Error—Bipolar Zero Error for
Gain Error Drift does not include Unipolar Offset Drift/Bipolar Zero Drift. It is effectively the drift of the part if zero-scale calibrations only were performed as is the case with background calibration.
These numbers are guaranteed by design and/or characterization.
The common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed.
The input voltage range on the analog inputs is given here with respect to the voltage on the respective negative input of its differential or pseudo-differential pair. See Table VII for which
V
These logic output levels apply to the MCLK OUT output only when it is loaded with a single CMOS load.
Sample tested at +25 C to ensure compliance.
See Burnout Current section.
After calibration, if the input voltage exceeds positive full scale, the converter will output all 1s. If the input is less than negative full scale, then the device outputs all 0s.
These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AV
For higher gains ( 8) at f
When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DV
Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 5 Hz, 10 Hz, 25 Hz or 50 Hz. PSRR at 60 Hz will exceed 120 dB with filter
PSRR depends on gain.
If the external master clock continues to run in standby mode, the standby current increases to 150 A typical with 5 V supplies and 75 A typical with 3.3 V supplies. When using a crystal
bipolar ranges.
inputs form differential pairs.
limit applies to both the unipolar zero point and the bipolar zero point.
type (see Clocking and Oscillator Circuit section).
notches of 6 Hz, 10 Hz, 30 Hz or 60 Hz.
or ceramic resonator across the MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation depends on the crystal or
resonator type (see Standby Mode section).
V
Floating State Leakage Current
Floating State Output Capacitance
D ata Output Coding
Current
Initial Tolerance
Drift
Positive Full-Scale Calibration Limit
Negative Full-Scale Calibration Limit
Offset Calibration Limit
Input Span
Power Supply Voltages
Power Supply Currents
Power Supply Rejection
Normal-Mode Power Dissipation
Normal-Mode Power Dissipation
Standby (Power-Down) Current
Standby (Power-Down) Current
REF
OH
AV
DV
AV
DV
= REF IN(+) – REF IN(–).
, Output High Voltage
DD
DD
DD
DD
Voltage
Current
Current
Voltage
16
18
CLK IN
19
16
= 2.4576 MHz, the BST bit of the Filter High Register must be set to 1. For other conditions, it can be set to 0.
Gain
AV
AV
14
DD
DD
21
21
= 3 V
= 5 V
18
13
15
15
1
86 dB
90 dB
Y Versions
DV
9
Offset Binary
1
0.1
(1.05 V
–(1.05 V
–(1.05 V
0.8
(2.1
+2.7 to +3.3 or
+4.75 to +5.25
+2.7 to +5.25
0.28
0.6
0.5
1.1
0.080
0.16
0.18
0.35
See Note 20
1.05
2.04
1.35
2.34
2.1
3.75
3.1
4.75
18
10
Binary
10
10
DD
V
– 0.6
V
REF
REF
REF
REF
REF
/GAIN
)/GAIN
)/GAIN
)/GAIN V max
)/GAIN V max
2
78 dB
78 dB
Units
V min
pF typ
% typ
%/ C typ
V max
V min
V max
V
V
V
mA max
mA max
mA max
mA max
mA max
mA max
mA max
mA max
dB typ
mW max
mW max
mW max
mW max
mW max
mW max
mW max
mW max
A max
A max
A max
A nom
–6–
4
85 dB
84 dB
Conditions/Comments
I
Unipolar Mode
Bipolar Mode
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
For Specified Performance
For Specified Performance
AV
Typically 0.22 mA. BUFFER = 0 V. f
Typically 0.45 mA. BUFFER = DV
AV
Typically 0.38 mA. BUFFER = 0 V. f
Typically 0.8 mA. BUFFER = DV
Digital I/Ps = 0 V or DV
Typically 0.06 mA. DV
Typically 0.13 mA. DV
Typically 0.15 mA. DV
Typically 0.3 mA. DV
AV
BST Bit of Filter High Register = 0
Typically 0.84 mW. BUFFER = 0 V. f
Typically 1.53 mW. BUFFER = +3 V. f
Typically 1.11 mW. BUFFER = 0 V. f
Typically 1.9 mW. BUFFER = +3 V. f
AV
Typically 1.75 mW. BUFFER = 0 V. f
Typically 2.9 mW. BUFFER = +5 V. f
Typically 2.6 mW. BUFFER = 0 V. f
Typically 3.75 mW. BUFFER = +5 V. f
External MCLK IN = 0 V or DV
External MCLK IN = 0 V or DV
SOURCE
DD
DD
DD
DD
= DV
= DV
= 3 V or 5 V. BST Bit of Filter High Register = 0
= 3 V or 5 V. BST Bit of Filter High Register = 1
DD
= 100 A with DV
DD
current and power dissipation will vary depending on the crystal or resonator
DD
DD
+ 30 mV or go more negative than AGND – 30 mV. The offset calibration
8–128
93 dB
91 dB
= +3 V. Digital I/Ps = 0 V or DV
= +5 V. Digital I/Ps = 0 V or DV
DD
DD
DD
DD
DD.
= 5 V. f
= 3 V. f
= 5 V. f
= 3 V. f
DD
External MCLK IN, CLKDIS = 1
= 3 V. Except for MCLK OUT
CLK IN
DD
DD
CLK IN
CLK IN
CLK IN
DD
17
. Typically 9 A. V
. Typically 4 A. V
DD
. f
CLK IN
CLK IN
CLK IN
. f
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
= 2.4576 MHz
CLK IN
CLK IN
CLK IN
= 1 MHz
= 1 MHz
= 2.4576 MHz
= 2.4576 MHz. BST Bit = 0
= 1 MHz or 2.4576 MHz
= 2.4576 MHz
= 1 MHz. BST Bit = 0
= 2.4576 MHz. BST Bit = 0
= 1 MHz. BST Bit = 0
= 2.4576 MHz. BST Bit = 0
= 1 MHz. BST Bit = 0
= 2.4576 MHz
= 1 MHz. BST Bit = 0
= 2.4576 MHz. BST Bit = 0
= 1 MHz or 2.4576 MHz
DD
DD
. External MCLK IN
. External MCLK IN
DD
DD
17
17
, CLKDIS = 1
= +5 V
= +3 V
12
REV. C