AD9271BSVZ-40 Analog Devices Inc, AD9271BSVZ-40 Datasheet - Page 30

• Manufacturer Part Number: AD9271BSVZ-40
• Description: IC ADC OCT 12BIT 40MSPS 100-TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9271BSVZ-40

• Data Interface: Serial, SPI™
• Number Of Bits: 12
• Sampling Rate (per Second): 40M
• Number Of Converters: 8
• Power Dissipation (max): 1.28W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad
• Resolution (bits): 12bit
• Sampling Rate: 50MSPS
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Digital: 1.7V To 1.9V
• Supply Current: 613mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9271-50EBZ - BOARD EVALUATION AD9271 50MSPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9271
Digital Outputs and Timing
The AD9271 differential outputs conform to the ANSI-644 LVDS
standard on default power-up. This can be changed to a low power,
reduced signal option similar to the IEEE 1596.3 standard by using
the SDIO pin or via the SPI. This LVDS standard can further
reduce the overall power dissipation of the device by approximately
36 mW. See the SDIO Pin section or Table 15 for more
information.
The LVDS driver current is derived on chip and sets the output
current at each output equal to a nominal 3.5 mA. A 100 Ω differ-
ential termination resistor placed at the LVDS receiver inputs
results in a nominal 350 mV swing at the receiver.
The AD9271 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs that have LVDS capability
for superior switching performance in noisy environments.
Single point-to-point net topologies are recommended with a
100 Ω termination resistor placed as close to the receiver as
possible. No far-end receiver termination and poor differential
trace routing may result in timing errors. It is recommended
that the trace length be no longer than 24 inches and that the
differential output traces be kept close together and at equal
lengths. An example of the FCO, DCO, and data stream with
proper trace length and position can be found in Figure 62.
An example of the LVDS output using the ANSI-644 standard
(default) data eye and a time interval error (TIE) jitter histogram
with trace lengths of less than 24 inches on regular FR-4 material
is shown in Figure 63. Figure 64 shows an example of the trace
lengths exceeding 24 inches on regular FR-4 material. Notice
that the TIE jitter histogram reflects the decrease of the data eye
opening as the edge deviates from the ideal position; therefore,
the user must determine if the waveforms meet the timing budget
of the design when the trace lengths exceed 24 inches.
Figure 62. LVDS Output Timing Example in ANSI-644 Mode (Default)
CH1 500mV/DIV Ω
CH2 500mV/DIV Ω
CH3 500mV/DIV Ω
5.0ns/DIV
Rev. B | Page 30 of 60
Additional SPI options allow the user to further increase the
internal termination (and therefore increase the current) of all
eight outputs in order to drive longer trace lengths (see Figure 65).
Even though this produces sharper rise and fall times on the
data edges, is less prone to bit errors, and improves frequency
distribution (see Figure 65), the power dissipation of the DRVDD
supply increases when this option is used.
In cases that require increased driver strength to the DCO± and
FCO± outputs because of load mismatch, Register 0x15 allows
the user to double the drive strength. To do this, first set the
appropriate bit in Register 0x05. Note that this feature cannot
be used with Bit 4 and Bit 5 in Register 0x15 because these bits
take precedence over this feature. See the Memory Map section
for more details.
Figure 63. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
–100
–200
–400
–600
600
400
200
100
–200ps
25
20
15
10
0
5
0
–1.5ns
of Less Than 24 Inches on Standard FR-4
EYE: ALL BITS
–1.0ns
–100ps
–0.5ns
0ps
0ns
0.5ns
ULS: 2398/2398
100ps
1.0ns
1.5ns
200ps