AD6654BBC Analog Devices Inc, AD6654BBC Datasheet - Page 55

IC ADC 14BIT W/6CH RSP 256CSPBGA

AD6654BBC

Manufacturer Part Number
AD6654BBC
Description
IC ADC 14BIT W/6CH RSP 256CSPBGA
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD6654BBC

Number Of Bits
14
Sampling Rate (per Second)
92.16M
Data Interface
Serial, Parallel
Number Of Converters
1
Power Dissipation (max)
2.5W
Voltage Supply Source
Analog and Digital
Operating Temperature
-25°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-CSPBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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MASTER/SLAVE PCLK MODES
The parallel ports can operate in either master or slave mode.
The mode is set via PCLK master mode bit in the Parallel Port
Control 2 register. The parallel ports power up in slave mode to
avoid possible contentions on the PCLK pin.
In master mode, PCLK is an output derived by dividing
PLL_CLK down by the PCLK divisor. The PCLK divisor can
have a value of 1, 2, 4, or 8, depending on the 2-bit PCLK
divisor word setting in the Parallel Port Control 2 register. The
highest PLCK rate in master mode is 200 MHz. Master mode is
PxCH [2:0]
Px [15:0]
PxGAIN
PxACK
PxREQ
PCLK
PxIQ
Figure 60. Parallel I/Q Mode with an AGC Gain Word
t
DPREQ
Rev. 0 | Page 55 of 88
t
t
t
DPP
DPIQ
Q [15:8]
DPCH
I [15:8]
selected by setting the PCLK master mode bit in the Parallel
Port Control 2 register.
In slave mode, external circuitry provides the PCLK signal.
Slave mode PCLK signals can be either synchronous or
asynchronous. The maximum slave mode PCLK frequency is
also 200 MHz.
PxCH [2:0] = CHANNEL #
PCLK
rate
GAIN [11:0]
t
DPGAIN
0000 +
=
PLL
PCLK
_
CLK
divisor
rate
AD6654

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