MAX113CAG+T Maxim Integrated Products, MAX113CAG+T Datasheet - Page 8

• Manufacturer Part Number: MAX113CAG+T
• Description: IC ADC 8BIT 400KSPS 24-SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX113CAG+T

• Number Of Bits: 8
• Sampling Rate (per Second): 400k
• Data Interface: Parallel
• Number Of Converters: 3
• Power Dissipation (max): 640mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In read mode, conversions and data access are con-
trolled by the RD input (Figure 3). The comparator
inputs track the analog input voltage for the duration of
t
low. With µPs that can be forced into a wait state, hold
RD low until output data appears. The µP starts the
conversion, waits, and then reads data with a single
read instruction.
In read mode, WR/RDY is configured as a status output
(RDY), so it can drive the ready or wait input of a µP.
RDY is an open-collector output (no internal pull-up)
that goes low after the falling edge of CS and goes high
at the end of the conversion. If not used, the WR/RDY
pin can be left unconnected. The INT output goes low
at the end of the conversion and returns high on the ris-
ing edge of CS or RD.
Figures 4 and 5 show the operating sequence for write-
read mode. The comparator inputs track the analog
input voltage for the duration of t
initiated by a falling edge of WR. When WR returns
high, the result of the four-MSBs flash is latched into the
output buffers and the conversion of the four-LSBs flash
starts. INT goes low, indicating conversion end, and the
lower four data bits are latched into the output buffers.
The data is then accessible after RD goes low (see
Timing Characteristics ).
A minimum acquisition time (t
going low to the start of another conversion (WR going
low).
Options for reading data from the converter include
using internal delay, reading before delay, and pipelined
operation (discussed in the following sections).
The µP waits for the INT output to go low before reading
the data (Figure 4). INT goes low after the rising edge of
WR, indicating that the conversion is complete and the
result is available in the output latch. With CS low, data
outputs D0–D7 can be accessed by pulling RD low. INT
is then reset by the rising edge of CS or RD.
An external method of controlling the conversion time is
shown in Figure 5. The internally generated delay
(t
age, and can be overridden with RD to achieve the
fastest conversion time. RD is brought low after the ris-
ing edge of WR, but before INT goes low. This com-
pletes the conversion and enables the output buffers
+3V, 400ksps, 4/8-Channel,
8-Bit ADCs with 1µA Power-Down
8
ACQ
INTL
_______________________________________________________________________________________
. A conversion is initiated by driving CS and RD
) varies slightly with temperature and supply volt-
Write-Read Mode (MODE = 1)
Read Mode (MODE = 0)
Reading Before Delay
Using Internal Delay
ACQ
Fastest Conversion:
ACQ
) is required from INT
. The conversion is
Figure 3. Read Mode Timing (Mode = 0)
Figure 4. Write-Read Mode Timing (t
Figure 5. Write-Read Mode Timing (t
D0–D7
A0–A2
PWRDN
D0–D7
A0–A2
D0–D7
A0–A2
WR
INT
CS
RD
RDY
WR
INT
CS
RD
INT
CS
RD
t
ACQ
t
CSS
t
ACQ
t
RDY
ADDRESS VALID
ADDRESS
VALID (N)
t
ADDRESS
VALID (N)
CSS
t
ACQ
t
UP
t
CSS
(N)
t
AH
t
AH
t
WR
t
WR
t
AH
t
WITH EXTERNAL
CSH
t
CSH
t
t
ACCO
t
CRD
PULL-UP
CWR
t
t
RD
INTL
t
INTL
t
ACC1
t
RD
t
CSS
t
ACC2
RD
RD
t
> t
< t
CSS
ADDRESS VALID (N + 1)
VALID DATA
t
ADDRESS VALID (N + 1)
READ1
INTL
ADDRESS VALID (N + 1)
INTL
(N)
VALID DATA
t
RI
t
t
READ2
VALID DATA
(N)
ACQ
) (Mode = 1)
t
) (Mode = 1)
ACQ
t
t
ACQ
CSH
t
INTH
(N)
t
DH
t
DH
t
DH
t
t
INTH
CSH
t
CSH
t
AH
t
INTH