AD7853ARS Analog Devices Inc, AD7853ARS Datasheet - Page 5

• Manufacturer Part Number: AD7853ARS
• Description: IC ADC 12BIT SRL 200KSPS 24-SSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7853ARS

• Rohs Status: RoHS non-compliant
• Number Of Bits: 12
• Sampling Rate (per Second): 200k
• Data Interface: 8051, QSPI™, Serial, SPI™ µP
• Number Of Converters: 2
• Power Dissipation (max): 33mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP (0.200", 5.30mm Width)

REV. B
TYPICAL TIMING DIAGRAMS
Figures 2 and 3 show typical read and write timing diagrams.
Figure 2 shows the reading and writing after conversion in In-
terface Modes 2 and 3. To attain the maximum sample rate of
100 kHz (AD7853L) or 200 kHz (AD7853) in Interface Modes
2 and 3, reading and writing must be performed during conver-
sion. Figure 3 shows the timing diagram for Interface Modes 4
and 5 with sample rate of 100 kHz (AD7853L) or 200 kHz
(AD7853). At least 400 ns acquisition time must be allowed
(the time from the falling edge of BUSY to the next rising edge
of CONVST) before the next conversion begins to ensure that
the part is settled to the 12-bit level. If the user does not want to
provide the CONVST signal, the conversion can be initiated in
software by writing to the control register.
Figure 2. AD7853/AD7853L Timing Diagram (Typical Read and Write Operation for Interface Modes 2, 3)
Figure 3. AD7853/AD7853L Timing Diagram (Typical Read and Write Operation for Interface Modes 4, 5)
CONVST (I/P)
CONVST (I/P)
BUSY (O/P)
DOUT (O/P)
BUSY (O/P)
SYNC (O/P)
DOUT (O/P)
SCLK (O/P)
SYNC (I/P)
SCLK (I/P)
DIN (I/P)
POLARITY PIN LOGIC HIGH
POLARITY PIN LOGIC HIGH
t
2
t
2
THREE-
STATE
t
1
t
1
t
5
t
8
DB15
t
7
t
CONVERT
t
4
THREE-
STATE
1
DB15
t
t
CONVERT
1
t
t
t
CONVERT
1
5
= 100 ns MIN,
= 100 ns MIN,
= 4.6 s MAX, 10 s FOR L VERSION
t
= 4.6 s MAX, 10 s FOR L VERSION
3
DB15
DB11
t
7
t
1
5
t
5
= 50/90 ns MAX 5V/3V,
= 50/90 ns MAX 5V/3V,
–5–
DB15
DB11
t
6
5
t
6
t
8
Figure 1. Load Circuit for Digital Output Timing
Specifications
t
t
CONVERT
9
t
6
10
DB11
DB0
t
t
TO OUTPUT
7
7
= 40/60 ns MIN 5V/3V
5
= 40/60 ns MIN 5V/3V
DB11
DB0
16
t
PIN
9
t
6
100pF
t
6
t
C
10
11
L
THREE-
STATE
DB0
16
1.6mA
200 A
t
12
AD7853/AD7853L
DB0
t
11
t
I
I
OL
OH
12
THREE-
STATE
+2.1V