X9250UV24IZ-2.7T2 Intersil, X9250UV24IZ-2.7T2 Datasheet - Page 8
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X9250UV24IZ-2.7T2
Manufacturer Part Number
X9250UV24IZ-2.7T2
Description
IC XDCP QUAD 256TP 50K 24-TSSOP
Manufacturer
Intersil
Series
XDCP™r
Datasheet
1.X9250US24.pdf
(20 pages)
Specifications of X9250UV24IZ-2.7T2
Taps
256
Resistance (ohms)
50K
Number Of Circuits
4
Temperature Coefficient
300 ppm/°C Typical
Memory Type
Non-Volatile
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-TSSOP
Resistance In Ohms
50K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 8. Increment/Decrement Timing Limits
Table 1. Instruction Set
Read Wiper Counter
Register
Write Wiper Counter
Register
Read Data Register
Write Data Register
XFR Data Register to
Wiper Counter Register
XFR Wiper Counter
Global XFR Data Register
to Wiper Counter Register
Global XFR Wiper Counter
Register to Data Register
Increment/Decrement
Wiper Counter Register
Read Status (WIP bit)
Register to Data Register
Instruction
V
W
SCK
/R
SI
W
INC/DEC CMD Issued
8
I
1
1
1
1
1
1
0
1
0
0
3
I
0
0
0
1
1
1
0
0
0
1
2
I
0
1
1
0
0
1
0
0
1
0
1
Instruction Set
I
1
0
1
0
1
0
1
0
0
1
0
Voltage Out
R
R
R
R
R
R
R
0
0
0
0
1
1
1
1
1
1
1
X9250
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
0
0
0
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
P
0
0
1
0
0
0
0
0
0
0
0
Read the contents of the Wiper Counter
Register pointed to by P
Write new value to the Wiper Counter Register
pointed to by P
Read the contents of the Data Register
pointed to by P
Write new value to the Data Register pointed to
by P
Transfer the contents of the Data Register
pointed to by R
Register pointed to by P
Transfer the contents of the Wiper Counter
Register pointed to by P
pointed to by R
Transfer the contents of the Data Registers
pointed to by R
respective Wiper Counter Register
Transfer the contents of all Wiper Counter
Registers to their respective data Registers
pointed to by R
Enable Increment/decrement of the Wiper
Counter Register pointed to by P
Read the status of the internal write cycle, by
checking the WIP bit.
t
WRID
1
- P
0
and R
1
1
1
1
1
1
- R
- P
- P
1
- R
- R
- R
- R
Operation
0
0
0
0
0
0
0
of all four pots to their
and R
to the Wiper Counter
of all four pots
1
1
1
- P
- P
- P
1
0
0
- R
0
to the Register
0
1
- P
0
August 29, 2006
FN8165.3