X9250US24Z-2.7 Intersil, X9250US24Z-2.7 Datasheet - Page 12

• Manufacturer Part Number: X9250US24Z-2.7
• Description: IC XDCP QUAD 256TP 50K 24-SOIC
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of X9250US24Z-2.7

• Taps: 256
• Resistance (ohms): 50K
• Number Of Circuits: 4
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
ENDURANCE AND DATA RETENTION
CAPACITANCE
POWER-UP TIMING
POWER UP AND DOWN REQUIREMENT
The are no restrictions on the sequencing of the bias supplies V
their final values within 1msec of each other. At all times, the voltages on the potentiometer pins must be less than V+
and more than V-. The recall of the wiper position from nonvolatile memory is not in effect until all supplies reach their
final value. The V
Notes: (5) This parameter is periodically sampled and not 100% tested
A.C. TEST CONDITIONS
Symbol
I nput pulse levels
Input rise and fall times
Input and output timing level
I
I
Symbol
V
C
t
CC1
CC2
I
I
V
V
Symbol
R
I
t
SB
LO
C
t
OL
OUT
PUW
LI
IH
PUR
IL
IN
V
(6) t
(7) Sample tested only.
CC
(5)
(5)
(6)
(6)
issued. These parameters are periodically sampled and not 100% tested.
(7)
PUR
Minimum endurance
V
(active)
V
(nonvolatile write)
V
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
Output LOW voltage
CC
CC
CC
and t
Data retention
Parameter
Output capacitance (SO)
Input capacitance (A0, A1, SI, and SCK, CS)
supply current
supply current
current (standby)
Power-up to initiation of read operation
Power-up to initiation of write operation
V
CC
PUW
Parameter
CC
ramp rate spec is always in effect.
are the delays required from the time the third (last) power supply (V
power up ramp rate
12
V
10ns
V
Parameter
CC
CC
Test
x 0.1 to V
x 0.5
V
CC
Min.
-0.5
x 0.7
CC
x 0.9
100,000
Typ.
Min.
100
X9250
Limits
V
V
CC
CC
Max.
400
0.4
10
10
1
5
+ 0.1
x 0.3
CC
, V+, and V- provided that all three supplies reach
Max.
Min.
8
6
0.2
Unit
mA
µA
µA
µA
µA
V
V
V
CC
, V+ or V-) is stable until the specific instruction can be
Data changes per bit per register
f
Other Inputs = V
f
Other Inputs = V
SCK = SI = V
V
V
I
SCK
SCK
OL
IN
OUT
Unit
= 3mA
= V
pF
pF
= 2MHz, SO = Open,
= 2MHz, SO = Open,
= V
Max.
SS
50
Years
1
5
Test Conditions
Unit
SS
to V
to V
SS
CC
, Addr. = V
SS
SS
Test Conditions
CC
V
V
OUT
IN
V/msec
= 0V
Unit
SS
= 0V
ms
ms
August 29, 2006
FN8165.3