X9250US24Z-2.7 Intersil, X9250US24Z-2.7 Datasheet - Page 6

• Manufacturer Part Number: X9250US24Z-2.7
• Description: IC XDCP QUAD 256TP 50K 24-SOIC
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of X9250US24Z-2.7

• Taps: 256
• Resistance (ohms): 50K
• Number Of Circuits: 4
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The four high order bits of the instruction byte specify
the operation. The next two bits (R
one of the four registers that is to be acted upon when
a register oriented instruction is issued. The last two
bits (P1 and P
potentiometers is to be affected by the instruction.
Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte.
These instructions are:
– XFR Data Register to Wiper Counter Register—This
– XFR Wiper Counter Register to Data Register—This
– Global XFR Data Register to Wiper Counter Regiter—
– Global XFR Wiper Counter Register to Data Regiter—
The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by t
from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of t
between one of the four potentiometers and one of its
associated registers; or it may occur globally, where
the transfer occurs between all potentiometers and one
associated register.
transfers the contents of one specified Data Register
to the associated Wiper Counter Register.
transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.
This transfers the contents of all specified Data Reg-
isters to the associated Wiper Counter Registers.
This transfers the contents of all Wiper Counter
Registers to the specified associated Data Regis-
ters.
WR
0
to complete. The transfer can occur
) selects which one of the four
6
1
WRL
and R
. A transfer
0
) select
X9250
Five instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9250; either between the host and
one of the data registers or directly between the host
and the Wiper Counter Register. These instructions
are:
– Read Wiper Counter Register—read the current
– Write Wiper Counter Register—change current
– Read Data Register—read the contents of the
– Write Data Register—write a new value to the
– Read Status—This command returns the contents
The sequence of these operations is shown in Figure
5 and Figure 6.
The final command is Increment/Decrement. It is
different from the other commands, because it’s length
is indeterminate. Once the command is issued, the
master can clock the selected wiper up and/or down in
one resistor segment steps; thereby, providing a fine
tuning capability to the host. For each SCK clock pulse
(t
one resistor segment towards the V
Similarly, for each SCK clock pulse while SI is LOW,
the selected wiper will move one resistor segment
towards the V
sequence and timing for this operation are shown in
Figure 7 and Figure 8.
HIGH
wiper position of the selected pot,
wiper position of the selected pot,
selected data register;
selected data register.
of the WIP bit which indicates if the internal write
cycle is in progress.
) while SI is HIGH, the selected wiper will move
L
/R
L
terminal. A detailed illustration of the
H
/R
H
August 29, 2006
terminal.
FN8165.3