DS1881E-050+ Maxim Integrated Products, DS1881E-050+ Datasheet - Page 13

• Manufacturer Part Number: DS1881E-050+
• Description: IC POT DIGIT DL NV 50K 16TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of DS1881E-050+

• Taps: 64
• Resistance (ohms): 45K
• Number Of Circuits: 2
• Temperature Coefficient: 750 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resistance In Ohms: 45K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

An example of writing to the DS1881 is shown in Figure 2.
The DS1881 has one write command that is used to
change the Potentiometer Wiper Setting registers and the
Configuration Register. All write operations begin with a
START from the master, followed by a slave address
byte. The R/W bit should be written to 0, which initiates
a write command. Once the slave address byte has
been issued and the master receives the acknowledge
from the DS1881, potentiometer wiper data is transmit-
ted to the DS1881 by the master device.
If the potentiometer has been configured to be written
in nonvolatile memory (see the Configuration Register
section), then the acknowledge needs to be followed
with a STOP command. This command is required from
the master at the end of data transmission to initiate the
EEPROM write. The STOP command is also accepted if
the user has configured the pot values to be written in
volatile memory, but no EEPROM is written to.
I
protocol with device addressing. A device that sends
data on the bus is defined as a transmitter, and a
device receiving data as a receiver. The device that
controls the message is called a master. The devices
that are controlled by the master are slaves. The bus
must be controlled by a master device that generates
the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions. The
DS1881 operates as a slave on the I
to the bus are made by the open-drain I/O lines, SDA
and SCL. The following I/O terminals control the I
serial port: CE, SDA, SCL, A0, A1, and A2. A data
transfer protocol and a timing diagram are provided in
Figures 3 and 4. The following terminology is commonly
used to describe I
Figure 2. Write Protocol
2
C interface supports a bidirectional data transmission
I 2 C Serial Interface Descriptions
MSB
0
Dual NV Audio Taper Digital Potentiometer
1 0 1
SLAVE ADDRESS
Writing Command Byte Values
2
BYTE
C data transfers.
A
2
A
1
R/W = 0
A
0
LSB
0
MSB
DATA BYTES CAN BE WRITTEN IN ANY ORDER.
2
0
C bus. Connections
____________________________________________________________________
0
COMMAND
BYTE
POT-0
LSB
WRITE PROTOCOL
2
C
MSB
0
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses, START and STOP conditions.
Slave Devices: Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy: Time between STOP and START
conditions when both SDA and SCL are inactive and in
their logic-high states. When the bus is idle it often initi-
ates a low-power mode for slave devices.
START Condition: A START condition is generated by
the master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a START condition. See the timing dia-
gram for applicable timing.
STOP Condition: A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL remains
high generates a STOP condition. See the timing dia-
gram for applicable timing.
Repeated START Condition: The master can use a
repeated START condition at the end of one data trans-
fer to indicate that it will immediately initiate a new data
transfer following the current one. Repeated STARTS
are commonly used during read operations to identify a
specific memory address to begin a data transfer. A
repeated START condition is issued identically to a nor-
mal START condition. See the timing diagram for
applicable timing.
Bit Write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold-time requirements (see Figure 4). Data is
shifted into the device during the rising edge of the SCL.
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount of
1
COMMAND
BYTE
POT-1
LSB
MSB
1 0
COMMAND
BYTE
CONFIG
REG
I
2
C Definitions
LSB
13