CY62128EV30LL-55SXET Cypress Semiconductor Corp, CY62128EV30LL-55SXET Datasheet

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CY62128EV30LL-55SXET

Manufacturer Part Number
CY62128EV30LL-55SXET
Description
CY62128EV30LL-55SXET
Manufacturer
Cypress Semiconductor Corp
Series
-r
Datasheet

Specifications of CY62128EV30LL-55SXET

Format - Memory
RAM
Memory Type
SRAM
Memory Size
1M (128K x 8)
Speed
55ns
Interface
Parallel
Voltage - Supply
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Package / Case
32-SOIC (0.445", 11.30mm Width)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
1-Mbit (128K x 8) Static RAM
Features
Note
Cypress Semiconductor Corporation
Document #: 001-65528 Rev. **
Logic Block Diagram
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at
Very high-speed: 45 ns
Temperature ranges:
Wide voltage range: 2.2 V to 3.6 V
Pin compatible with CY62128DV30
Ultra low standby power
Ultra low active power
Easy memory expansion with CE
Automatic power down when deselected
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
Offered in Pb-free 32-pin small outline integrated circuit (SOIC),
32-pin thin small outline package (TSOP I), and 32-pin STSOP
packages
Automotive-A: –40 °C to +85 °C
Automotive-E: –40 °C to +125 °C
Typical standby current: 1 A
Maximum standby current: 4 A
Typical active current: 1.3 mA at f = 1 MHz
CE 2
CE 1
WE
OE
1
, CE
A 0
A 1
A 2
A 3
A 10
A 11
A 4
A 5
A 6
A 7
A 8
A 9
2,
and OE features
198 Champion Court
COLUMN DECODER
INPUT BUFFER
128K x 8
ARRAY
Functional Description
The CY62128EV30
module organized as 128K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL
applications such as cellular telephones. The device also has an
automatic power-down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device in standby mode reduces power consumption by more
than 99 percent when deselected (CE
eight input and output pins (I/O
high-impedance state when the device is deselected (CE
or CE
operation is in progress (CE
LOW).
To write to the device, take Chip Enable (CE
HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins is then written into the location specified on the Address pin
(A
To read from the device, take Chip Enable (CE
HIGH) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
0
POWER
DOWN
1-Mbit (128K x 8) Static RAM
through A
2
CY62128EV30 MoBL
LOW), the outputs are disabled (OE HIGH), or a write
San Jose
16
).
http://www.cypress.com.
[1]
,
is a high performance CMOS static RAM
CA 95134-1709
1
LOW and CE
0
through I/O
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
1
Revised January 6, 2011
HIGH or CE
®
Automotive
7
2
) are placed in a
1
1
HIGH and WE
LOW and CE
LOW and CE
408-943-2600
®
2
) in portable
LOW). The
1
HIGH
2
2
[+] Feedback

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CY62128EV30LL-55SXET Summary of contents

Page 1

... Note 1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at Cypress Semiconductor Corporation Document #: 001-65528 Rev. ** CY62128EV30 MoBL 1-Mbit (128K x 8) Static RAM Functional Description The CY62128EV30 module organized as 128K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ ...

Page 2

Contents Pin Configuration ............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics.................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 Data Retention Characteristics ........................................ 5 Switching Characteristics ................................................ 6 Switching Waveforms ...................................................... 7 Truth Table .................................................................. 8 ...

Page 3

... Table 1. Product Portfolio Product Range Min CY62128EV30LL Auto-A CY62128EV30LL Auto-E Table 2. Pin Definitions Input A –A . Address inputs 0 16 Input/output I/O –I/O . Data lines. Used as input or output lines depending on operation 0 7 Input/control WE. Write Enable, Active LOW. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is conducted ...

Page 4

... Document #: 001-65528 Rev. ** CY62128EV30 MoBL Output current into outputs (LOW) .............................. 20 mA Static discharge voltage.......................................... > 2001 V (MIL-STD-883, Method 3015) Latch up current...................................................... > 200 mA Operating Range Device + 0.3 V CC(max) CY62128EV30LL + 0.3 V CC(max) + 0.3 V CC(max (Auto-A) Test Conditions Min = –0.1 mA, V < 2. –1.0 mA, V > ...

Page 5

... Conditions  0 > 0.2 V < 0 > < 0 CY62128EV30LL-45 CY62128EV30LL- spec. Other inputs can be left floating. SB2 CCDR > 100 s or stable CC(min) CC(min) ® Automotive Max Unit SOIC STSOP 33.01 48.67 32.56 ° 3.42 25 ...

Page 6

Switching Characteristics (Over the Operating Range) Parameter [14, 15] Description Read Cycle t Read cycle time RC t Address to data valid AA t Data hold from address change OHA t CE LOW to data valid ACE ...

Page 7

Switching Waveforms Figure 6. Read Cycle 1 Address transition controlled Address Data Out Previous Data Valid Figure 7. Read Cycle No controlled Address CE t ACE OE t LZOE High Impedance DATA OUT t LZCE ...

Page 8

Switching Waveforms (continued) Figure 9. Write Cycle No. 2 CE1 or CE2 controlled ADDRESS CE WE DATA I/O Figure 10. Write Cycle No controlled, OE LOW ADDRESS NOTE 31 DATA I/O t HZWE Truth ...

Page 9

... Ordering Information Speed Ordering Code (ns) 45 CY62128EV30LL-45SXA CY62128EV30LL-45ZXA CY62128EV30LL-45ZAXA 55 CY62128EV30LL-55ZXE CY62128EV30LL-55SXE Contact your local Cypress sales representative for availability of these parts. Ordering Code Definition CY 621 2 8E V30 LL 45/55 XXX Document #: 001-65528 Rev. ** CY62128EV30 MoBL Package Package Type Diagram 51-85081 32-pin 450-Mil SOIC (Pb-free) ...

Page 10

Package Diagrams Figure 11. 32-Pin (450 Mil) Molded SOIC, 51-85081 Document #: 001-65528 Rev. ** ® CY62128EV30 MoBL Automotive 51-85081-*C Page [+] Feedback ...

Page 11

Package Diagrams (continued) Figure 12. 32-Pin Thin Small Outline Package Type mm), 51-85056 Document #: 001-65528 Rev. ** ® CY62128EV30 MoBL Automotive 51-85056-*E Page [+] Feedback ...

Page 12

Package Diagrams (continued) Figure 13. 32-Pin Shrunk Thin Small Outline Package (8 x 13.4 mm), 51-85094 Acronyms Acronym Description CMOS complementary metal oxide semiconductor I/O input/output SOIC small outline integrated circuit SRAM static random access memory TSOP thin small outline ...

Page 13

Document History Page ® Document Title: CY62128EV30 MoBL Document Number: 001-65528 Rev. ECN No. Submission Date ** 3115909 01/06/2011 Document #: 001-65528 Rev. ** CY62128EV30 MoBL Automotive 1-Mbit (128K x 8) Static RAM Orig. of Description of Change Change RAME ...

Page 14

... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...

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