CY62128EV30LL-55SXET Cypress Semiconductor Corp, CY62128EV30LL-55SXET Datasheet - Page 6

• Manufacturer Part Number: CY62128EV30LL-55SXET
• Description: CY62128EV30LL-55SXET
• Manufacturer: Cypress Semiconductor Corp
• Series: -r

Specifications of CY62128EV30LL-55SXET

• Format - Memory: RAM
• Memory Type: SRAM
• Memory Size: 1M (128K x 8)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-SOIC (0.445", 11.30mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Switching Characteristics
(Over the Operating Range)
Notes
Document #: 001-65528 Rev. **
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
14. CE is the logical combination of CE
15. Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of V
16. At any given temperature and voltage condition, t
17. t
18. The internal write time of the memory is defined by the overlap of WE, CE = V
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
Parameter
levels of 0 to V
a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
HZOE
, t
HZCE
V
CE
CC
[18]
, and t
[14, 15]
CC(typ)
HZWE
, and output loading of the specified I
Read cycle time
Address to data valid
Data hold from address change
CE LOW to data valid
OE LOW to data valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-up
CE HIGH to Power-down
Write cycle time
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
Data setup to write end
Data Hold from write end
WE LOW to High Z
WE HIGH to Low Z
transitions are measured when the output enter a high impedance state.
1
and CE
Description
2
. When CE
V
[16]
[16]
[16, 17]
[16, 17]
[16]
HZCE
[16,17]
t
CC(min)
CDR
Figure 5. Data Retention Waveform
is less than t
1
is LOW and CE
OL
/I
OH
as shown in the
LZCE
DATA RETENTION MODE
, t
2
HZOE
is HIGH, CE is LOW; when CE
IL
. All signals must be ACTIVE to initiate a write and any of these signals can terminate
is less than t
“AC Test Loads and Waveforms”
V
DR
Min
45
10
10
45
35
35
35
25
10
45 ns (Auto-A)
–
–
–
5
–
–
0
–
0
0
0
–
> 1.5V
CY62128EV30 MoBL
LZOE
, and t
[14]
Max
45
45
22
18
18
45
18
–
–
–
–
–
–
–
–
–
–
–
–
–
–
HZWE
1
is HIGH or CE
is less than t
on page 5.
V
CC(min)
Min
55
10
10
55
40
40
40
25
10
t
–
–
–
5
–
–
0
–
0
0
0
–
LZWE
R
55 ns (Auto-E)
2
is LOW, CE is HIGH.
for any given device.
®
Max
Automotive
55
55
25
20
20
55
20
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CC(typ)
Page 6 of 14
/2, input pulse
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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