CAT5132ZI-10-GT3 ON Semiconductor, CAT5132ZI-10-GT3 Datasheet - Page 11

• Manufacturer Part Number: CAT5132ZI-10-GT3
• Description: IC POT DPP 15V 128TAP I2C 10MSOP
• Manufacturer: ON Semiconductor

Specifications of CAT5132ZI-10-GT3

• Taps: 128
• Resistance (ohms): 10K
• Number Of Circuits: 1
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resistance In Ohms: 10K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data Register (DR)
contents are automatically written to the Wiper Control
Register (WCR) on power−up. It can be read at any time
without effecting the value of the WCR. The DR, like the
WCR, only stores the 7 LSB bits and will report the MSB bit
as a “0”. Writing to the DR is performed in the same fashion
as the WCR except that a time delay of up to 5 ms is
experienced while the nonvolatile store operation is being
performed. During the internal non−volatile write cycle, the
device ignores transitions at the SDA and SCL pins, and the
SDA output is at a high impedance state. The WCR is also
followed by a valid slave address byte, a valid address byte
00h, a second Start and a second slave address byte for read.
After each of the three bytes the CAT5132 responds with an
Table 17. DR WRITE OPERATION
Table 18. DR READ OPERATION
ST
ST
ST
ST
ST
The Data Register (DR) is a nonvolatile register and its
A read operation (see Table 18) requires a Start condition,
0
0
0
0
0
1
1
1
1
1
slave address byte
slave address byte
slave address byte
0
0
0
0
0
1st byte
1st byte
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
A
A
A
A
A
0
0
0
0
0
0
0
0
0
X
DR address − 00h
DR address − 00h
AR address − 02h
AR address − 02h
http://onsemi.com
0
0
0
0
X
data byte
2nd byte
2nd byte
0
0
0
0
X
11
X
0
0
0
0
written during a write to DR. After a DR WRITE is complete
the DR and WCR will contain the same wiper position.
selected, see table 1 then the data is written or read using the
following sequences.
followed by a valid slave address byte, a valid address byte
00h, a data byte and a STOP condition. After each of the
three bytes the CAT5132 responds with an acknowledge. At
this time the data is written both to volatile and non−volatile
registers, then the device enters its standby state.
acknowledge and then the device transmits the data byte.
The master terminates the read operation by issuing a STOP
condition following the last bit of Data byte.
X
0
0
0
0
To write or read to the DR, first the access to DR is
A write operation (see Table 17) requires a Start condition,
X
1
0
1
0
X
0
0
0
0
A
A
A
SP
X
0
0
X
0
0
DR(00h) selection
DR(00h) selection
X
0
0
data byte
3rd byte
3rd byte
X
0
0
0
X
0
0
X
0
X
0
0
X
0
0
A
A
A
SP
SP
SP