CAT5132ZI-10-GT3 ON Semiconductor, CAT5132ZI-10-GT3 Datasheet - Page 9

• Manufacturer Part Number: CAT5132ZI-10-GT3
• Description: IC POT DPP 15V 128TAP I2C 10MSOP
• Manufacturer: ON Semiconductor

Specifications of CAT5132ZI-10-GT3

• Taps: 128
• Resistance (ohms): 10K
• Number Of Circuits: 1
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resistance In Ohms: 10K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Description
Access Control Register
DR are accessed only by addressing the volatile Access
Register AR first, using the 3 byte I
and write operations (see Table 12). The first byte is the slave
address/instruction byte (see details below). The second
byte contains the address (02h) of the AR register. The data
in the third byte controls which register WCR (80h) or DR
(00h) is being addressed (see Figure 10).
Slave Address Instruction Byte Description
processor is called the Slave/DPP Address Byte. The most
significant five bits of the slave address are a device type
identifier. For the CAT5132 these bits are fixed at 01010
(refer to Table 13).
Table 12. ACCESS CONTROL REGISTER
Table 13. BYTE 1 SLAVE ADDRESS AND INSTRUCTION BYTE
ST
ST
The volatile register WCR and the non−volatile register
The first byte sent to the CAT5132 from the master
0
0
1
1
(MSB)
ID4
0
0
0
1st byte
1
1
BUS ACTIVITY:
0
0
ID3
SDA LINE
1
MASTER
0
0
0
0
Figure 10. Access Register Addressing Using 3 Bytes
Device Type Identifier
2
0
0
C protocol for all read
S
T
A
R
T
S
ID2
A
A
0
FIXED
& INSTRUCTION
0
0
VARIABLE
ADDRESS
SLAVE
0
0
AR address − 02h
http://onsemi.com
ID1
0
0
1
2nd byte
A
C
K
0
0
0
0
9
AR REGISTER
ADDRESS
address and must match the physical device address which
is defined by the state of the A1 and A0 input pins. Only the
device with slave address matching the input byte will be
accessed by the master. This allows up to 4 devices to reside
on the same bus. The A1 and A0 inputs can be actively
driven by CMOS input signals or tied to V
function to be performed. If it is a “1” a read command is
initiated and if it is a “0” a write is initiated. For the AR
register only write is allowed.
address byte, the CAT5132 monitors the bus and responds
with an acknowledge when its address matches the
transmitted slave address.
0
0
ID0
0
The next two bits, A1 and A0, are the internal slave
The last bit is the READ/WRITE bit and determines the
After the Master sends a START condition and the slave
1
1
0
0
A
C
K
A
A
SELECTION
A1
Slave Address
X
WCR/DR
1
0
WCR(80h) / DR(00h) selection
0
0
0
0
A
C
K
A0
X
3rd byte
S
O
P
P
T
0
0
0
0
Read/Write
0
0
(LSB)
R/W
CC
0
0
X
or Ground.
0
0
A
A
SP
SP