CAT5132ZI-10-GT3 ON Semiconductor, CAT5132ZI-10-GT3 Datasheet - Page 8

• Manufacturer Part Number: CAT5132ZI-10-GT3
• Description: IC POT DPP 15V 128TAP I2C 10MSOP
• Manufacturer: ON Semiconductor

Specifications of CAT5132ZI-10-GT3

• Taps: 128
• Resistance (ohms): 10K
• Number Of Circuits: 1
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resistance In Ohms: 10K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Bus Protocol
processor or controller, and the device being controlled is the
slave. The master will always initiate data transfers and
provide the clock for both transmit and receive operations.
Therefore, the CAT5132 will be considered a slave device
in all applications.
START Condition
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH. The CAT5132 monitors the SDA and
SCL lines and will not respond until this condition is met
(see Figure 8).
STOP Condition
determines the STOP condition. All operations must end
with a STOP condition (see Figure 8).
The following defines the features of the I
The device controlling the transfer is a master, typically a
The START Condition precedes all commands to the
A LOW to HIGH transition of SDA when SCL is HIGH
FROM TRANSMITTER
1. Data transfer may be initiated only when the bus is
2. During a data transfer, the data line must remain
FROM RECEIVER
not busy.
stable whenever the clock line is high. Any
changes in the data line while the clock is high
will be interpreted as a START or STOP condition.
DATA OUTPUT
DATA OUTPUT
SCL FROM
MASTER
SDA
SCL
START
BUS RELEASE DELAY (TRANSMITTER)
CONDITION
START
1
2
Figure 9. Acknowledge Condition
C bus protocol:
Figure 8. Start/Stop Condition
ACK DELAY (≤ t
http://onsemi.com
8
AA
)
8
Acknowledge
required to generate an acknowledge. The acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data (see Figure 9).
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8−bit
byte.
of data, releases the SDA line, and monitors the line for an
acknowledge. Once it receives this acknowledge, the
CAT5132 will continue to transmit data. If no acknowledge
is sent by the Master, the device terminates data transmission
and waits for a STOP condition.
Acknowledge Polling
of the typical write cycle time. Once the STOP condition is
issued to indicate the end of the write operation, the
CAT5132 initiates the internal write cycle. ACK polling can
be initiated immediately. This involves issuing the START
condition followed by the slave address. If the CAT5132 is
still busy with the write operation, no ACK will be returned.
If the CAT5132 has completed the write operation, an ACK
will be returned and the host can then proceed with the next
instruction operation.
After a successful data transfer, each receiving device is
The CAT5132 responds with an acknowledge after
When the CAT5132 is in a READ mode it transmits 8 bits
The disabling of the inputs can be used to take advantage
9
ACK SETUP (≥ t
CONDITION
STOP
BUS RELEASE DELAY (RECEIVER)
SU:DAT
)