TWR-K53N512-KIT Freescale Semiconductor, TWR-K53N512-KIT Datasheet - Page 25

• Manufacturer Part Number: TWR-K53N512-KIT
• Description: TWR-K53N512 Dev Kit
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr
• Type: MCUr

Specifications of TWR-K53N512-KIT

• Kit Contents: TWR-K53N512 - 32bit MCU Module With MK53N512CMD100 & TWRPI-SLCD Daughter Card, DVD With IDE Software
• Mcu Supported Families: K50
• Kit Features: MK53N512CMD100 MAPBGA 144 Pins MCU, Tower
• Rohs Compliant: Yes
• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Tower System

4.5 Module-by-module feature list
The following sections describe the high-level module features for the family's superset device. See the previous section for
differences among the subset devices.
4.5.1
4.5.1.1 ARM Cortex-M4 Core
4.5.1.2 Nested Vectored Interrupt Controller (NVIC)
4.5.1.3 Wake-up Interrupt Controller (WIC)
4.5.1.4 Debug Controller
Freescale Semiconductor, Inc.
• Supports up to 100 MHz frequency with 1.25DMIPS/MHz
• ARM Core based on the ARMv7 Architecture & Thumb
• Microcontroller cores focused on very cost sensitive, deterministic, interrupt driven environments
• Harvard bus architecture
• 3-stage pipeline with branch speculation
• Integrated bus matrix
• Integrated Digital Signal Processor (DSP)
• Configurable nested vectored interrupt controller (NVIC)
• Advanced configurable debug and trace components
• Embedded Trace Macrocell (ETM)
• Close coupling with Cortex-M4 core's Harvard architecture enables low latency interrupt handling
• Up to 120 interrupt sources
• Includes a single non-maskable interrupt
• 16 levels of priority, with each interrupt source dynamically configurable
• Supports nesting of interrupts when higher priority interrupts are activated
• Relocatable vector table
• Supports interrupt handling when system clocking is disabled in low power modes
• Takes over and emulates the NVIC behavior when correctly primed by the NVIC on entry to very-deep-sleep
• A rudimentary interrupt masking system with no prioritization logic signals for wake-up as soon as a non-masked
• Contains no programmer’s model visible state and is therefore invisible to end users of the device other than through
• Serial Wire JTAG Debug Port (SWJ-DP) combines
• Debug Watchpoint and Trace (DWT) with the following functionality:
interrupt is detected
the benefits of reduced power consumption while sleeping
• external interface that provides a standard JTAG or cJTAG interface for debug access
• external interface that provides a serial-wire bidirectional debug interface
• four comparators configurable as a hardware watchpoint, an ETM trigger, a PC sampler event trigger, or a data
Core modules
address sampler event trigger
K50 Family Product Brief, Rev. 8, 5/2011
®
-2 ISA
Core modules
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