TWR-K53N512-KIT Freescale Semiconductor, TWR-K53N512-KIT Datasheet - Page 36

• Manufacturer Part Number: TWR-K53N512-KIT
• Description: TWR-K53N512 Dev Kit
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr
• Type: MCUr

Specifications of TWR-K53N512-KIT

• Kit Contents: TWR-K53N512 - 32bit MCU Module With MK53N512CMD100 & TWRPI-SLCD Daughter Card, DVD With IDE Software
• Mcu Supported Families: K50
• Kit Features: MK53N512CMD100 MAPBGA 144 Pins MCU, Tower
• Rohs Compliant: Yes
• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Tower System

Power modes
5 Power modes
The power management controller (PMC) provides the user with multiple power options. All together 10 different modes of
operation are supported to allow the user to optimize power consumption for the level of functionality needed.
Depending on the stop requirements of the user application, a variety of stop modes are available that provide state retention,
partial power down or full power down of certain logic and/or memory. I/O states are held in all modes of operation. The
following table compares the various power modes available.
For each run mode there is a corresponding wait and stop mode. Wait modes are similar to ARM sleep modes. Stop modes
(VLPS, STOP) are similar to ARM sleep deep mode. The very low power run (VLPR) operating mode can drastically reduce
runtime power when the maximum bus frequency is not required to handle the application needs.
The three primary modes of operation are run, wait and stop. The WFI instruction invokes both wait and stop modes for the
chip. The primary modes are augmented in a number of ways to provide lower power based on application needs.
36
Normal Stop -
Normal Wait -
Chip mode
Normal run
• Programmable LCD frame frequency
• Programmable blink modes and frequency
• Programmable LCD power supply switch, making it an ideal solution for battery-powered and board-level applications
• Internal-regulated voltage source with a 4-bit trim register to apply contrast control
• Integrated charge pump for generating LCD bias voltages
• Waveform storage registers
• Backplane reassignment to assist in vertical scrolling on dot-matrix displays
• Software-configurable LCD frame frequency interrupt
via WFI
via WFI
• Generate up to 44 frontplane signals
• Generate up to 8 backplanes signals
• All segments blank during blink period
• Alternate display for each LCD segment in x4 or less mode
• Blink operation in low-power modes
• Charge pump requires only four external capacitors
• Internal LCD power using VDD
• Internal VIREG regulated power supply option for 3 V or 5 V LCD glass
• External VLL3 power supply option (3 V)
• Hardware-configurable to drive 3 V or 5 V LCD panels
• On-chip generation of bias voltages
Allows maximum performance of chip. Default mode out of reset; on-
chip voltage regulator is on.
Allows peripherals to function while the core is in sleep mode,
reducing power. NVIC remains sensitive to interrupts; peripherals
continue to be clocked.
Places chip in static state. Lowest power mode that retains all
registers while maintaining LVD protection. NVIC is disabled; AWIC is
used to wake up from interrupt; peripheral clocks are stopped.
Description
Table 7. Chip power modes
Table continues on the next page...
K50 Family Product Brief, Rev. 8, 5/2011
Sleep Deep
Core mode
Freescale Semiconductor, Inc.
Sleep
Run
recovery
Interrupt
Interrupt
method
Normal
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