AD5641AKSZ-500RL7 Analog Devices Inc, AD5641AKSZ-500RL7 Datasheet - Page 4

IC DAC 14BIT V-OUT SC70-6

AD5641AKSZ-500RL7

Manufacturer Part Number
AD5641AKSZ-500RL7
Description
IC DAC 14BIT V-OUT SC70-6
Manufacturer
Analog Devices Inc
Series
nanoDAC™r
Datasheet

Specifications of AD5641AKSZ-500RL7

Data Interface
SPI™
Settling Time
6µs
Number Of Bits
14
Number Of Converters
1
Voltage Supply Source
Single Supply
Power Dissipation (max)
550µW
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
SC-70-6, SC-88, SOT-363
Resolution (bits)
14bit
Sampling Rate
1.7MSPS
Input Channel Type
Serial
Supply Voltage Range - Analog
2.7V To 5.5V
Supply Current
75µA
Digital Ic Case Style
SC-70
Number Of Channels
1
Resolution
14b
Conversion Rate
1.7MSPS
Interface Type
Serial (3-Wire, SPI, QSPI, Microwire)
Single Supply Voltage (typ)
3.3/5V
Dual Supply Voltage (typ)
Not RequiredV
Architecture
Resistor-String
Power Supply Requirement
Single
Output Type
Voltage
Integral Nonlinearity Error
±16LSB
Single Supply Voltage (min)
2.7V
Single Supply Voltage (max)
5.5V
Dual Supply Voltage (min)
Not RequiredV
Dual Supply Voltage (max)
Not RequiredV
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
6
Package Type
SC-70
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
AD5641AKSZ-500RL7TR
AD5641AKSZ500RLTR
AD5641AKSZ500RLTR
AD5641
TIMING CHARACTERISTICS
V
Table 3.
Parameter
t
t
t
t
t
t
t
t
t
1
2
1
2
3
4
5
6
7
8
9
All input signals are specified with t
Maximum SCLK frequency is 30 MHz.
DD
2
= 2.7 V to 5.5 V; all specifications T
SYNC
SCLK
SDIN
Limit
33
5
5
10
5
4.5
0
20
13
R
1
= t
t
8
F
= 1 ns/V (10% to 90% of V
t
4
D15
MIN
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
to T
D14
MAX
t
3
, unless otherwise noted. See Figure 2.
t
2
DD
) and timed from a voltage level of (V
Figure 2. Timing Diagram
t
Test Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to next SCLK falling edge ignored
1
Rev. C | Page 4 of 20
D2
t
5
D1
t
6
D0
t
7
IL
t
9
+ V
IH
)/2.
D15
D14

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