AD5310BRMZ Analog Devices Inc, AD5310BRMZ Datasheet - Page 4

• Manufacturer Part Number: AD5310BRMZ
• Description: IC DAC 10BIT R-R W/BUFF 8-MSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5310BRMZ

• Data Interface: Serial
• Settling Time: 6µs
• Number Of Bits: 10
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 1.25mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Resolution (bits): 10bit
• Sampling Rate: 167kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 2.7V To 5.5V
• Supply Current: 140µA
• Digital Ic Case Style: SOP
• Package: 8MSOP
• Resolution: 10 Bit
• Conversion Rate: 167 KSPS
• Architecture: Resistor-String
• Digital Interface Type: Serial (3-Wire, SPI, QSPI, Microwire)
• Number Of Outputs Per Chip: 1
• Output Type: Voltage
• Full Scale Error: -1.25 %FSR
• Integral Nonlinearity Error: ±4 LSB
• Maximum Settling Time: 8 us
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD5310
SOT-23 Pin Numbers
Pin
No.
1
2
3
4
5
6
Mnemonic
V
GND
V
DIN
SCLK
SYNC
OUT
DD
Analog output voltage from DAC. The output amplifier has rail-to-rail operation.
Ground reference point for all circuitry on the part.
Power Supply Input. These parts can be operated from +2.5 V to +5.5 V and V
coupled to GND.
Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the
falling edge of the serial clock input.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates up to 30 MHz.
Level triggered control input (active low). This is the frame synchronization signal for the input
data. When SYNC goes low, it enables the input shift register and data is transferred in on the
falling edges of the following clocks. The DAC is updated following the 16th clock cycle unless
SYNC is taken high before this edge in which case the rising edge of SYNC acts as an interrupt and
the write sequence is ignored by the DAC.
Function
V
GND
V
OUT
DD
1
2
3
(Not to Scale)
SOT-23
TOP VIEW
AD5310
PIN FUNCTION DESCRIPTIONS
6
5
4
PIN CONFIGURATIONS
SYNC
SCLK
DIN
–4–
V
V
OUT
NC
NC
DD
NC = NO CONNECT
1
2
3
4
(Not to Scale)
TOP VIEW
AD5310
SOIC
8
7
6
5
SYNC
GND
SCLK
DIN
DD
should be de-
REV. A