AD5310BRMZ Analog Devices Inc, AD5310BRMZ Datasheet - Page 8

• Manufacturer Part Number: AD5310BRMZ
• Description: IC DAC 10BIT R-R W/BUFF 8-MSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5310BRMZ

• Data Interface: Serial
• Settling Time: 6µs
• Number Of Bits: 10
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 1.25mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Resolution (bits): 10bit
• Sampling Rate: 167kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 2.7V To 5.5V
• Supply Current: 140µA
• Digital Ic Case Style: SOP
• Package: 8MSOP
• Resolution: 10 Bit
• Conversion Rate: 167 KSPS
• Architecture: Resistor-String
• Digital Interface Type: Serial (3-Wire, SPI, QSPI, Microwire)
• Number Of Outputs Per Chip: 1
• Output Type: Voltage
• Full Scale Error: -1.25 %FSR
• Integral Nonlinearity Error: ±4 LSB
• Maximum Settling Time: 8 us
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD5310
GENERAL DESCRIPTION
D/A Section
The AD5310 DAC is fabricated on a CMOS process. The
architecture consists of a string DAC followed by an output
buffer amplifier. Since there is no reference input pin, the
power supply (V
block diagram of the DAC architecture.
Since the input coding to the DAC is straight binary, the ideal
output voltage is given by:
where D = decimal equivalent of the binary code which is
loaded to the DAC register; it can range from 0 to 1023.
DAC REGISTER
R
R
R
R
R
DD
Figure 20. DAC Architecture
DB15 (MSB)
Figure 21. Resistor String
X
) acts as the reference. Figure 20 shows a
V
OUT
X
V
PD1
DD
RESISTOR
REF (+)
REF (–)
STRING
GND
V
DD
PD 0
1024
D
TO OUTPUT
AMPLIFIER
0
0
1
1
D9
0
1
0
1
OUTPUT
AMPLIFIER
Figure 22. Input Register Contents
D8
NORMAL OPERATION
1k
100k
THREE-STATE
TO GND
TO GND
D7
V
OUT
D6
POWER-DOWN MODES
–8–
D5
DATA BITS
Resistor String
The resistor string section is shown in Figure 21. It is simply a
string of resistors, each of value R. The code loaded to the DAC
register determines at what node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is guaran-
teed monotonic.
Output Amplifier
The output buffer amplifier is capable of generating rail-to-rail
voltages on its output which gives an output range of 0 V to
V
1000 pF to GND. The source and sink capabilities of the output
amplifier can be seen in Figures 8 and 9. The slew rate is 1 V/ s
with a half-scale settling time of 6 s with the output loaded.
SERIAL INTERFACE
The AD5310 has a three-wire serial interface (SYNC, SCLK
and DIN) which is compatible with SPI, QSPI and MICROWIRE
interface standards as well as most DSPs. See Figure 1 for a
timing diagram of a typical write sequence.
The write sequence begins by bringing the SYNC line low. Data
from the DIN line is clocked into the 16-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 30 MHz making the AD5310 compatible with high speed
DSPs. On the sixteenth falling clock edge, the last data bit is
clocked in and the programmed function is executed (i.e., a
change in DAC register contents and/or a change in the mode of
operation). At this stage, the SYNC line may be kept low or be
brought high. In either case, it must be brought high for a mini-
mum of 33 ns before the next write sequence so that a falling
edge of SYNC can initiate the next write sequence. Since the
SYNC buffer draws more current when V
when V
sequences for even lower power operation of the part. As is
mentioned above, however, it must be brought high again just
before the next write sequence.
Input Shift Register
The input shift register is 16 bits wide (see Figure 22). The first
two bits are “don’t cares.” The next two are control bits which
control which mode of operation the part is in (normal mode or
any one of three power-down modes). There is a more complete
description of the various modes in the Power-Down Modes
section. The next ten bits are the data bits. These are transferred
to the DAC register on the sixteenth falling edge of SCLK. Finally,
the last two bits are “don’t cares.”
DD
. It is capable of driving a load of 2 k in parallel with
D4
IN
= 0.8 V, SYNC should be idled low between write
D3
D2
D1
D0
X
DB0 (LSB)
IN
= 2.4 V than it does
X
REV. A