CS43L21-CNZ Cirrus Logic Inc, CS43L21-CNZ Datasheet - Page 30

• Manufacturer Part Number: CS43L21-CNZ
• Description: IC DAC 24BIT 98DB 96KHZ 32QFN
• Manufacturer: Cirrus Logic Inc

Specifications of CS43L21-CNZ

• Package / Case: 32-QFN
• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 96 KSPS
• Resolution: 24 bit
• Interface Type: Serial
• Operating Supply Voltage: 1.8 V or 2.5 V
• Operating Temperature Range: + 70 C
• Mounting Style: SMD/SMT
• Number Of Dac Outputs: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1282 - BOARD EVAL FOR CS43L21 DAC
• Power Dissipation (max): -
• Settling Time: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1187

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4.4.3
4.4.4
4.5
LRCK
SCLK
SDIN
Digital Interface Formats
The serial port operates in standard I²S, Left-Justified or Right-Justifieddigital interface formats with varying
bit depths from 16 to 24. Data is clocked into the DAC on the rising edge of SCLK.
the general structure of each format. Refer to
timing relationship between clocks and data.
Hardware
High-Impedance Digital Output
The serial port may be placed on a clock/data bus that allows multiple masters for the SCLK/LRCK I/O
without the need for external buffers. The 3ST_SP bit places the internal buffers for these I/O in a high-
impedance state, allowing another device to transmit clocks without bus contention.
Quarter- and Half-Speed Mode
Quarter-Speed Mode (QSM) and Half-Speed Mode (HSM) allow lower sample rates while maintaining a
relatively flat noise floor in the typical audio band of 20 Hz - 20 kHz. Single-Speed Mode (SSM) will allow
lower frequency sample rates; however, the DAC's noise floor, that normally rises out-of-band, will scale
with the lower sample rate and begin to rise within the audio band. QSM and HSM corrects for most of
this scaling, effectively increasing the dynamic range of the CODEC at lower sample rates, relative to
SSM.
Software
Control:
Control:
M S B
“Interface Control (Address 04h)” on page
AOUTA / AINxA
“I²S/LJ” pin 3
L eft C h a n n e l
Transmitting Device #1
Pin
CS42L51
Figure 13. Tri-State SCLK/LRCK
3ST_SP
Setting
Figure 14. I²S Format
L S B
LO
HI
Receiving Device
SCLK/LRCK
“Switching Specifications - Serial Port” on page 16
Left-Justified Interface
I²S Interface
41.
M S B
Transmitting Device #2
AOUTB / AINxB
R ig ht C h a n n el
Selection
Figures 14-17
L S B
CS43L21
DS723A1
for exact
illustrate
MSB