CS43L21-CNZ Cirrus Logic Inc, CS43L21-CNZ Datasheet - Page 39

• Manufacturer Part Number: CS43L21-CNZ
• Description: IC DAC 24BIT 98DB 96KHZ 32QFN
• Manufacturer: Cirrus Logic Inc

Specifications of CS43L21-CNZ

• Package / Case: 32-QFN
• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 96 KSPS
• Resolution: 24 bit
• Interface Type: Serial
• Operating Supply Voltage: 1.8 V or 2.5 V
• Operating Temperature Range: + 70 C
• Mounting Style: SMD/SMT
• Number Of Dac Outputs: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1282 - BOARD EVAL FOR CS43L21 DAC
• Power Dissipation (max): -
• Settling Time: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1187

DS723A1
6. REGISTER DESCRIPTION
All registers are read/write except for the chip I.D. and Revision Register and Interrupt Status Register which are
read only. See the following bit definition tables for bit assignment information. The default state of each bit after a
power-up sequence or reset is listed in each bit description.
All “Reserved” registers must maintain their default state.
6.1
6.2
Notes:
Reserved
Chip_ID4
7
7
Chip I.D. and Revision Register (Address 01h) (Read Only)
Chip I.D. (Chip_ID[4:0])
Default: 11011
Function:
I.D. code for the CS43L21. Permanently set to 11011.
Chip Revision (Rev_ID[2:0])
Default: 001
Function:
CS43L21 revision level. Revision B is coded as 001. Revision A is coded as 000.
Power Control 1 (Address 02h)
1. To activate the power-down sequence for individual channels (A or B,) both channels must first be pow-
2. Reserved bits 1 - 4 should always be set “high” by the user to minimize power consumption during nor-
Recommended channel power-down sequence: 1.) Enable the PDN bit, 2.) enable power-down for the se-
lect channels, 3.) disable the PDN bit.
Power Down DAC X (PDN_DACX)
Default: 0
0 - Disable
1 - Enable
Function:
DAC channel x will either enter a power-down or muted state when this bit is enabled. See
ered down either by enabling the PDN bit or by enabling the power-down bits for both channels. En-
abling the power-down bit on an individual channel basis after the D/A has fully powered up will mute
the selected channel without achieving any power savings.
mal operation.
PDN_DACB
Chip_ID3
6
6
PDN_DACA
Chip_ID2
5
5
Reserved
Chip_ID1
4
4
Reserved
Chip_ID0
3
3
Reserved
Rev_ID2
2
2
Reserved
Rev_ID1
1
1
Note 1
CS43L21
Rev_ID0
PDN
above.
0
0
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