AD9704BCPZ Analog Devices Inc, AD9704BCPZ Datasheet - Page 30

• Manufacturer Part Number: AD9704BCPZ
• Description: IC DAC TX 8BIT 175MSPS 32-LFCSP
• Manufacturer: Analog Devices Inc
• Series: TxDAC®r

Specifications of AD9704BCPZ

• Data Interface: Serial
• Settling Time: 11ns
• Number Of Bits: 8
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 50mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Resolution (bits): 8bit
• Sampling Rate: 175MSPS
• Input Channel Type: Parallel
• Supply Current: 5.1mA
• Digital Ic Case Style: CSP
• No. Of Pins: 32
• Supply Voltage Range - Analogue: 3.3V To 3.6V
• Rohs Compliant: Yes
• Number Of Channels: 1
• Resolution: 8b
• Interface Type: Parallel
• Single Supply Voltage (typ): 1.8/3.3V
• Architecture: Segment
• Power Supply Requirement: Analog and Digital
• Output Type: Current
• Integral Nonlinearity Error: ±0.09LSB
• Single Supply Voltage (min): 1.7V
• Single Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Package Type: LFCSP EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9704/AD9705/AD9706/AD9707
A logic high on Pin 17 (PIN/SPI/RESET), followed by a logic
low, resets the SPI port timing to the initial state of the
instruction cycle. This is true regardless of the present state of
the internal registers or the other signal levels present at the
inputs to the SPI port. If the SPI port is in the midst of an
instruction cycle or a data transfer cycle, none of the present
data is written.
The remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9704/
AD9705/AD9706/AD9707 and the system controller. Phase 2 of
the communication cycle is a transfer of one, two, three, or four
data bytes, as determined by the instruction byte. Using one
multibyte transfer is the preferred method. Single byte data
transfers are useful to reduce CPU overhead when register access
requires one byte only. Registers change immediately upon
writing to the last bit of each transfer byte.
Instruction Byte
The instruction byte contains the information shown in the
following bit map:
Table 13.
MSB
7
R/W
R/ W , Bit 7 of the instruction byte, determines whether a read or
a write data transfer occurs after the instruction byte write. Logic 1
indicates a read operation. Logic 0 indicates a write operation.
N1 and N0, Bit 6 and Bit 5 of the instruction byte, determine the
number of bytes to be transferred during the data transfer cycle.
The bit decodes are shown in Table 14.
A4, A3, A2, A1, and A0, which are Bit 4, Bit 3, Bit 2, Bit 1, and
Bit 0 of the instruction byte, respectively, determine which register
is accessed during the data transfer portion of the communication
cycle. For multibyte transfers, this address is the starting byte
address. The remaining register addresses are generated by the
AD9704/AD9705/AD9706/AD9707, based on the DATADIR bit
(Register 0x00, Bit 6).
Table 14. Byte Transfer Count
N1
0
0
1
1
Serial Interface Port Pin Descriptions
SCLK—Serial Clock. The serial clock pin is used to synchronize
data to and from the AD9704/AD9705/AD9706/AD9707 and to
run the internal state machines. The SCLK maximum frequency
is 20 MHz. All data input to the AD9704/AD9705/AD9706/
AD9707 is registered on the rising edge of SCLK. All data is
driven out of the AD9704/AD9705/AD9706/AD9707 on the
falling edge of SCLK.
6
N1
N0
0
1
0
1
5
N0
Description
Transfer 1 byte
Transfer 2 bytes
Transfer 3 bytes
Transfer 4 bytes
4
A4
3
A3
2
A2
1
A1
LSB
0
A0
Rev. A | Page 30 of 52
CSB—Chip Select. Active low input starts and gates a communica-
tion cycle. It allows more than one device to be used on the same
serial communications lines. The SDIO pin goes to a high imped-
ance state when this input is high. Chip select must stay low
during the entire communication cycle.
SDIO—Serial Data I/O. This pin is used as a bidirectional data
line to transmit and receive data.
MSB/LSB Transfers
The AD9704/AD9705/AD9706/AD9707 serial port can support
both most significant bit (MSB) first or least significant bit
(LSB) first data formats. This functionality is controlled by the
DATADIR bit (Register 0x00, Bit 6). The default is MSB first
(DATADIR = 0).
When DATADIR = 0 (MSB first), the instruction and data bytes
must be written from most significant bit to least significant bit.
Multibyte data transfers in MSB first format start with an
instruction byte that includes the register address of the most
significant data byte. Subsequent data bytes should follow in
order from high address to low address. In MSB first mode, the
serial port internal byte address generator decrements for each
data byte of the multibyte communication cycle.
When DATADIR = 1 (LSB first), the instruction and data bytes
must be written from least significant bit to most significant bit.
Multibyte data transfers in LSB first format start with an instruction
byte that includes the register address of the least significant data
byte followed by multiple data bytes. The serial port internal byte
address generator increments for each byte of the multibyte
communication cycle.
The AD9704/AD9705/AD9706/AD9707 serial port controller
data address decrements from the data address written toward
0x00 for multibyte I/O operations if the MSB first mode is
active. The serial port controller address increments from the
data address written toward 0x1F for multibyte I/O operations
if the LSB first mode is active.
Notes on Serial Port Operation
The AD9704/AD9705/AD9706/AD9707 serial port configura-
tion is controlled by Register 0x00, Bit 7. It is important to note
that the configuration changes immediately upon writing to the
last bit of the register. For multibyte transfers, writing to this
register can occur during the middle of communication cycle.
Care must be taken to compensate for this new configuration
for the remaining bytes of the current communication cycle.
The same considerations apply to setting the software reset,
SWRST (Register 0x00, Bit 5). All registers are set to their default
values except Register 0x00, which remains unchanged.
Use of single byte transfers is recommended when changing
serial port configurations or initiating a software reset to
prevent unexpected device behavior.