CS4341A-KSZ Cirrus Logic Inc, CS4341A-KSZ Datasheet - Page 10

• Manufacturer Part Number: CS4341A-KSZ
• Description: IC DAC STER 24BIT 192KHZ 16SOIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4341A-KSZ

• Package / Case: 16-SOIC
• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 90mW
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 192 KSPS
• Resolution: 24 bit
• Interface Type: Serial
• Operating Supply Voltage: 3.3 V or 5 V
• Operating Temperature Range: + 70 C
• Maximum Power Dissipation: 125 mW
• Mounting Style: SMD/SMT
• Number Of Dac Outputs: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1633

3.7
The CS4341A uses Popguard
and power-down. This technology, when used with external DC-blocking capacitors in series with the au-
dio outputs, minimizes the audio transients commonly produced by single-ended single-supply converters.
It is activated inside the DAC when the PDN bit or the RST pin is enabled/disabled and requires no other
external control, aside from choosing the appropriate DC-blocking capacitors.
3.8
As with any high resolution converter, the CS4341A requires careful attention to power supply and
grounding arrangements if its potential performance is to be realized. Figure 1 shows the recommended
power arrangements, with VA connected to a clean supply. If the ground planes are split between digital
ground and analog ground, REF_GND & AGND should be connected to the analog ground plane.
Decoupling capacitors should be as close to the DAC as possible, with the low value ceramic capacitor
being the closest. To further minimze impedance, these capacitors should be located on the same layer as
the DAC.
All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwant-
ed coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must
be positioned to minimize the electrical path from FILT+ to REF_GND (and VQ to REF_GND), and
should also be located on the same layer as the DAC. The CDB4341A evaluation board demonstrates the
optimum layout and power supply arrangements.
10
Popguard
When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to
AGND. Following a delay of approximately 1000 sample periods, each output begins to ramp to-
ward the quiescent voltage. Approximately 10,000 LRCK cycles later, the outputs reach V
audio output begins. This gradual voltage ramping allows time for the external DC-blocking capac-
itors to charge to the quiescent voltage, minimizing the power-up transient.
To prevent transients at power-down, the device must first enter its power-down state by enabling
RST or PDN. When this occurs, audio output ceases and the internal output buffers are disconnect-
ed from AOUTL and AOUTR. In their place, a soft-start current sink is substituted which allows
the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the
device may be turned off and the system is ready for the next power-on.
To prevent an audio transient at the next power-on, it is necessary to ensure that the DC-blocking
capacitors have fully discharged before turning on the power or exiting the power-down state. If
not, a transient will occur when the audio outputs are initially clamped to AGND. The time that the
device must remain in the power-down state is related to the value of the DC-blocking capacitance.
For example, with a 3.3 µF capacitor, the minimum power-down time will be approximately 0.4
seconds.
Grounding and Power Supply Arrangements
3.7.1
3.7.2
3.7.3
Power-up
Power-down
Discharge Time
®
Transient Control
®
technology to minimize the effects of output transients during power-up
CS4341A
DS582F2
Q
and