CS4341A-KSZ Cirrus Logic Inc, CS4341A-KSZ Datasheet - Page 17

• Manufacturer Part Number: CS4341A-KSZ
• Description: IC DAC STER 24BIT 192KHZ 16SOIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4341A-KSZ

• Package / Case: 16-SOIC
• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 90mW
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 192 KSPS
• Resolution: 24 bit
• Interface Type: Serial
• Operating Supply Voltage: 3.3 V or 5 V
• Operating Temperature Range: + 70 C
• Maximum Power Dissipation: 125 mW
• Mounting Style: SMD/SMT
• Number Of Dac Outputs: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1633

5.
NOTE: All registers are read/write in I
5.1
5.2
DS582F2
Reserved
AMUTE
5.1.1 SPEED MODE CONTROL (MC)
5.1.2 AUTO-DETECT DEFEAT (AUTOD)
5.1.3 MCLK DIVIDE-BY-2 (MCLKDIV)
REGISTER DESCRIPTION
7
0
7
1
MODE CONTROL 1 (ADDRESS 00H)
MODE CONTROL 2 (ADDRESS 01H)
Function:
Default = 00
00 - Single-Speed Mode
01 - Double-Speed Mode
10 - Quad-Speed Mode
The operational speed mode must be set if the auto-detect defeat bit is enabled (AUTOD = 1). These
bits are ignored if the auto-detect defeat is disabled (AUTOD = 0).
Default = 0
0 - Disabled
1 - Enabled
The Auto-Detect function can be defeated to allow sample rate changes from 50 to 84 kHz, and from
100 to 170 kHz. The operational speed mode must be set via the speed mode control bits (see section
5.1.1) if the auto-detect feature is defeated.
Default = 0
0 - Disabled
1 - Enabled
The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2.
DIF2
MC1
6
0
6
0
MC0
DIF1
2
C mode and write only in SPI mode, unless otherwise stated.
5
0
5
0
BIT 5-6
BIT 1
Reserved
BIT 2
DIF0
4
0
4
0
Reserved
DEM1
3
0
3
0
AUTOD
DEM0
2
0
2
0
MCLKDIV
POR
1
0
1
1
CS4341A
Reserved
PDN
0
0
0
1
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