CS4341A-KSZ Cirrus Logic Inc, CS4341A-KSZ Datasheet - Page 9

• Manufacturer Part Number: CS4341A-KSZ
• Description: IC DAC STER 24BIT 192KHZ 16SOIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4341A-KSZ

• Package / Case: 16-SOIC
• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 90mW
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 192 KSPS
• Resolution: 24 bit
• Interface Type: Serial
• Operating Supply Voltage: 3.3 V or 5 V
• Operating Temperature Range: + 70 C
• Maximum Power Dissipation: 125 mW
• Mounting Style: SMD/SMT
• Number Of Dac Outputs: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1633

3.5
The device includes on-chip digital de-emphasis. The Mode Control 2 bits select either the 32, 44.1, or 48
kHz de-emphasis filter. Figure 5 shows the de-emphasis curve for F
response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. Please see
section 5.2.3 for the desired de-emphasis control.
NOTE: De-emphasis is only available in Single-Speed Mode.
3.6
DS582F2
L R C K
S C L K
LR C K
S C LK
S D IN
S D IN
M S B
De-Emphasis Control
Recommended Power-up
1. Hold RST low until the power supply is stable, and the master and left/right clocks are locked to
the appropriate frequences, as discussed in section 3.3. In this state, the control port is reset to its
default settings and VQ will remain low.
2. Bring RST high. The device will remain in a low power state with VQ low.
3. Load the desired register settings while keeping the PDN bit set to 1.
4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µS
when the POR bit is set to 0. If the POR bit is set to 1, see section 3.7 for a complete description
of power-up timing.
M S B
-1 -2 -3 -4 -5
L S B
+1 +2 +3 +4 +5
3 2 c lo ck s
L e ft C h a n n e l
+ 5 + 4
L e ft C h a n n e l
Figure 3. Left Justified up to 24-Bit Data
+ 3 +2 + 1
-10dB
Gain
0dB
dB
Figure 4. Right Justified Data
Figure 5. De-Emphasis Curve
-7
LS B
-6 -5 -4 -3 -2 -1
3.183 kHz
T1=50 µs
F1
M S B
10.61 kHz
F2
M S B
Sequence
-1 -2 -3 -4
T2 = 15 µs
Frequency
L S B
+1 +2 +3 +4 +5
s
equal to 44.1 kHz. The frequency
+ 5 +4
R ig h t C h a n n e l
R ig h t C h a n n e l
+ 3 + 2 + 1
LS B
-7
-6 -5 -4 -3 -2 -1
CS4341A
M S B
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