CS4385-DQZ Cirrus Logic Inc, CS4385-DQZ Datasheet - Page 32

• Manufacturer Part Number: CS4385-DQZ
• Description: IC DAC 8CH 114DB 192KHZ 48LQFP
• Manufacturer: Cirrus Logic Inc

Specifications of CS4385-DQZ

• Data Interface: Serial
• Number Of Bits: 24
• Number Of Converters: 8
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 520mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Resolution (bits): 24bit
• Sampling Rate: 192kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 4.75V To 5.25V
• Supply Current: 84mA
• Digital Ic Case Style: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1154 - BOARD EVAL FOR CS4385 DAC
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1649

32
4.12.2 Software Mode
4.13
4.14
4.14.1 MAP Auto Increment
4.14.2 I²C Mode
Recommended Procedure for Switching Operational Modes
For systems where the absolute minimum in clicks and pops is required, it is recommended that the MUTE
bits are set prior to changing significant DAC functions (such as changing sample rates or clock sources).
The mute bits may then be released after clocks have settled and the proper modes have been set.
It is required to have the device held in reset if the minimum high/low time specs of MCLK cannot be met
during clock source changes.
Control Port Interface
The control port is used to load all the internal register settings in order to operate in Software Mode (see
Section 7. “Filter Plots” on page
the audio sample rate. However, to avoid potential interference problems, the control port pins should re-
main static if no operation is required.
The control port operates in one of two modes: I²C or SPI.
1. Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the
2. Bring RST high. The device will remain in a low power state with FILT+ low for 512 LRCK cycles in
3. In order to reduce the chances of clicks and pops, perform a write to the CP_EN bit prior to the
4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µs.
The device has MAP (memory address pointer) auto-increment capability enabled by the INCR bit (also
the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I²C writes or reads and
SPI writes. If INCR is set to 1, MAP will auto-increment after each byte is written, allowing block reads or
writes of successive registers.
In the I²C Mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial
control port clock, SCL (see
enables the user to alter the chip address (001100[AD0][R/W]) and should be tied to VLC or GND, as re-
quired, before powering up the device. If the device ever detects a high-to-low transition on the AD0/CS
pin after power-up, SPI Mode will be selected.
appropriate frequencies, as discussed in
settings, FILT+ will remain low, and VQ will be connected to VA/2.
Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-
Speed Mode).
completion of approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-
Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode). The desired register settings can be
loaded while keeping the PDN bit set to 1. Set the RMP_UP and RMP_DN bits to 1; then set the
format and mode control bits to the desired settings.
If more than the stated range of LRCK cycles passes before CPEN bit is written, the chip will enter
Hardware Mode and begin to operate with the M0-M4 as the mode settings. CPEN bit may be written
at anytime, even after the Hardware sequence has begun. It is advised that if the CPEN bit cannot be
set in time, the SDINx pins should remain static low (this way no audio data can be converted
incorrectly by the Hardware Mode settings).
Figure 26
48). The operation of the control port may be completely asynchronous with
for the clock to data relationship). There is no CS pin. The AD0 pin
Section
4.1. In this state, the registers are reset to the default
CS4385
DS671F2