CS4385-DQZ Cirrus Logic Inc, CS4385-DQZ Datasheet - Page 37

• Manufacturer Part Number: CS4385-DQZ
• Description: IC DAC 8CH 114DB 192KHZ 48LQFP
• Manufacturer: Cirrus Logic Inc

Specifications of CS4385-DQZ

• Data Interface: Serial
• Number Of Bits: 24
• Number Of Converters: 8
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 520mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Resolution (bits): 24bit
• Sampling Rate: 192kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 4.75V To 5.25V
• Supply Current: 84mA
• Digital Ic Case Style: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1154 - BOARD EVAL FOR CS4385 DAC
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1649

DS671F2
6. REGISTER DESCRIPTION
Note: All registers are read/write in I²C Mode and write only in SPI, unless otherwise noted.
6.1
6.1.1 Part Number ID (PART) [Read Only]
6.2
6.2.1 Control Port Enable (CPEN)
6.2.2 Freeze Controls (FREEZE)
PART4
CPEN
0
0
7
7
Chip Revision (address 01h)
Mode Control 1 (address 02h)
00001- CS4385
Revision ID (REV) [Read Only]
000 - Revision A0
001 - Revision B0
Function:
This read-only register can be used to identify the model and revision number of the device.
Default = 0
0 - Disabled
1 - Enabled
Function:
This bit defaults to 0, allowing the device to power-up in Stand-Alone Mode. The Control Port Mode can
be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the reg-
isters, and the pin definitions will conform to Control Port Mode. To accomplish a clean power-up, the user
should write this bit within 10 ms following the release of Reset.
Default = 0
0 - Disabled
1 - Enabled
Function:
This function allows modifications to be made to the registers without the changes taking effect until the
FREEZE is disabled. To make multiple changes in the Control port registers take effect simultaneously,
enable the FREEZE Bit, make all register changes, then Disable the FREEZE bit.
FREEZE
PART3
6
0
6
0
DSD/PCM
PART2
5
0
5
0
DAC4_DIS
PART1
0
0
4
4
DAC3_DIS
PART0
3
1
3
0
DAC2_DIS
REV2
2
2
0
-
DAC1_DIS
REV1
0
1
1
-
CS4385
REV0
PDN
0
0
1
-
37