AD5762RCSUZ Analog Devices Inc, AD5762RCSUZ Datasheet - Page 23

• Manufacturer Part Number: AD5762RCSUZ
• Description: IC DAC DUAL 16BIT 1LSB 32-TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD5762RCSUZ

• Data Interface: Serial
• Settling Time: 8µs
• Number Of Bits: 16
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital, Dual ±
• Power Dissipation (max): 180mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Resolution (bits): 16bit
• Sampling Rate: 84.6MSPS
• Input Channel Type: Serial
• Supply Voltage Range - Digital: 2.7V To 5.25V
• Supply Current: 4.25mA
• Digital Ic Case Style: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

See Figure 41 for a simplified block diagram of the DAC load
circuitry.
TRANSFER FUNCTION
Table 7 and Table 8 show the ideal input code to output voltage
relationship for both offset binary data coding and twos
complement data coding, respectively.
Table 7. Ideal Output Voltage to Input Code Relationship—Offset Binary Data Coding
MSB
1111
1000
1000
0111
0000
Table 8. Ideal Output Voltage to Input Code Relationship—Twos Complement Data Coding
MSB
0111
0000
0000
1111
1000
REFA, REFB
Figure 41. Simplified Serial Interface of Input Loading Circuitry
LDAC
SYNC
SCLK
SDIN
1111
0000
0000
1111
0000
1111
0000
0000
1111
0000
for One DAC Channel
INTERFACE
REGISTER
REGISTER
16-BIT
Digital Input
Digital Input
DAC
INPUT
LOGIC
DAC
I/V AMPLIFIER
1111
0000
0000
1111
0000
1111
0000
0000
1111
0000
OUTPUT
SDO
VOUTx
LSB
1111
0001
0000
1111
0000
LSB
1111
0001
0000
1111
0000
Rev. A | Page 23 of 32
Analog Output
V
+2 V
+2 V
0 V
−2 V
−2 V
Analog Output
V
+2 V
+2 V
0 V
−2 V
−2 V
OUT
OUT
The output voltage expression for the AD5762R is given by
where:
D is the decimal equivalent of the code loaded to the DAC.
V
ASYNCHRONOUS CLEAR (CLR)
CLR is a negative edge triggered clear that allows the outputs to
be cleared to either 0 V (twos complement coding) or negative
full scale (offset binary coding). It is necessary to maintain CLR low
for a minimum amount of time (see
to complete. When the
remains at the cleared value until a new value is programmed. If
CLR is at 0 V at power-on, all DAC outputs are updated with the
clear value. A clear can also be initiated through software by
writing the command of 0x04XXXX to the AD5762R.
REFIN
REFIN
REFIN
REFIN
REFIN
REFIN
REFIN
REFIN
REFIN
× (32,767/32,768)
× (1/32,768)
× (1/32,768)
× (32,767/32,768)
× (32,767/32,768)
× (1/32,768)
× (1/32,768)
× (32,767/32,768)
V
is the reference voltage applied at the REFA, REFB pins.
OUT
=
−
2
×
V
REFIN
CLR signal is returned high, the output
+
4
×
V
REFIN
Figure 2
⎡
⎢
⎣
65
,
D
536
) for the operation
⎤
⎥
⎦
AD5762R