CS4351-DZZ Cirrus Logic Inc, CS4351-DZZ Datasheet - Page 29

• Manufacturer Part Number: CS4351-DZZ
• Description: IC DAC STER 112DB 192KHZ 20TSSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS4351-DZZ

• Data Interface: Serial
• Number Of Bits: 24
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 354mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Resolution (bits): 24bit
• Sampling Rate: 192kSPS
• Input Channel Type: Serial
• Supply Current: 15mA
• Digital Ic Case Style: TSSOP
• No. Of Pins: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1152 - BOARD EVAL FOR CS4351 DAC
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

DS566F1
6.6.2
6.6.3
6.6.4
6.7
PDN
7
1
Misc Control - Register 08h
Soft Ramp and Zero Cross
Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or mut-
ing, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will
occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample
rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored
and implemented for each channel.
Soft Volume Ramp-Up After Error (RMP_UP) Bit 5
Function:
When set to 1 (default), an un-mute will be performed after executing a filter mode change, after a
LRCK/MCLK ratio change or error, and after changing the Functional Mode. This un-mute is affected, sim-
ilar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register.
When set to 0, an immediate un-mute is performed in these instances.
Note:
Soft Ramp-Down Before Filter Mode Change (RMP_DN) Bit 4
Function:
When set to 1 (default), a mute will be performed prior to executing a filter mode change. This mute is
affected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control
register.
When set to 0, an immediate mute is performed prior to executing a filter mode change.
Note:
Interpolation Filter Select (FILT_SEL) Bit 2
Function:
When set to 0 (default), the Interpolation Filter has a fast roll off.
When set to 1, the Interpolation Filter has a slow roll off.
The specifications for each filter can be found in the
sponse” section on page
CPEN
For best results, it is recommended this feature be used in conjunction with the RMP_DN bit.
For best results, it is recommended that this feature be used in conjunction with the RMP_UP bit.
6
0
FREEZE
5
0
8, and response plots can be found in
Reserved
4
0
Reserved
“Combined Interpolation & On-Chip Analog Filter Re-
3
0
Figures 15
Reserved
2
0
to 36.
Reserved
1
0
CS4351
Reserved
0
0
29