AD5024BRUZ Analog Devices Inc, AD5024BRUZ Datasheet

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AD5024BRUZ

Manufacturer Part Number
AD5024BRUZ
Description
IC DAC QUAD 12BIT 1LSB 16-TSSOP
Manufacturer
Analog Devices Inc
Series
nanoDAC™r
Datasheet

Specifications of AD5024BRUZ

Data Interface
SPI™
Settling Time
8µs
Number Of Bits
12
Number Of Converters
4
Voltage Supply Source
Single Supply
Power Dissipation (max)
30mW
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
16-TSSOP
Resolution (bits)
12bit
Sampling Rate
125kSPS
Input Channel Type
Serial
Supply Voltage Range - Analog
4.5V To 5.5V
Supply Current
4mA
Digital Ic Case Style
TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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FEATURES
Low power quad 12-/14-/16-bit DAC, ±1 LSB INL
Pin compatible and performance upgrade to
Individual and common voltage reference pin options
Rail-to-rail operation
4.5 V to 5.5 V power supply
Power-on reset to zero scale or midscale
3 power-down functions and per-channel power-down
Hardware LDAC with software LDAC override function
CLR function to programmable code
SDO daisy-chaining option
14-/16-lead TSSOP
Internal reference buffer and internal output amplifier
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5024/AD5044/AD5064/AD5064-1 are low power, quad
12-/14-/16-bit buffered voltage output nanoDAC® converters
that offer relative accuracy specifications of 1 LSB INL and 1 LSB
DNL with the AD5024/AD5044/AD5064 individual reference
pin and the AD5064-1 common reference pin options. The
AD5024/AD5044/AD5064/AD5064-1 can operate from a single
4.5 V to 5.5 V supply. The AD5024/AD5044/AD5064/AD5064-1
also offer a differential accuracy specification of ±1 LSB. The
parts use a versatile 3-wire, low power Schmitt trigger serial
interface that operates at clock rates up to 50 MHz and is compati-
ble with standard SPI, QSPI™, MICROWIRE™, and DSP interface
standards. Integrated reference buffers and output amplifiers are
also provided on-chip. The AD5024/AD5044/AD5064/AD5064-1
incorporate a power-on reset circuit that ensures the DAC
output powers up to zero scale or midscale and remains there
until a valid write takes place to the device. The AD5024/AD5044/
AD5064/AD5064-1 contain a power-down feature that reduces
the current consumption of the device to typically 400 nA at 5 V
and provides software selectable output loads while in power-
down mode. Total unadjusted error for the parts is <2 mV.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Fully Accurate, 12-/14-/16-Bit V
AD5666
SPI Interface, 4.5 V to 5.5 V in TSSOP
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
Table 1. Related Devices
Part No.
AD5666
AD5025/AD5045/AD5065
AD5062,
AD5061
AD5040/AD5060
Figure 1. AD5064-1 Functional Equivalent and Pin Compatible with AD5666
SCLK
SYNC
SCLK
SYNC
SDO
DIN
DIN
Figure 2. AD5024/AD5044/AD5064 with Individual Reference Pins
Quad channel available in 14-/16-lead TSSOP packages.
16-bit accurate, 1 LSB INL.
High speed serial interface with clock speeds up to 50 MHz.
Reset to known output voltage (zero scale or midscale).
AD5064-1
AD5024/
AD5044/
AD5064
AD5063
LDAC
INTERFACE
LOGIC AND
LDAC
INTERFACE
LOGIC AND
REGISTER
REGISTER
AD5024/AD5044/AD5064
FUNCTIONAL BLOCK DIAGRAMS
SHIFT
SHIFT
LDAC
LDAC
CLR
CLR
©2008–2010 Analog Devices, Inc. All rights reserved.
POWER-ON
REGISTER
REGISTER
REGISTER
REGISTER
POWER-ON
REGISTER
REGISTER
REGISTER
REGISTER
INPUT
INPUT
INPUT
INPUT
RESET
INPUT
INPUT
INPUT
INPUT
RESET
POR
POR
V
V
DD
DD
Description
Quad,16-bit buffered DAC,
16 LSB INL, TSSOP
Dual, 16-bit buffered DACs,
1 LSB INL, TSSOP
16-bit nanoDAC, 1 LSB INL, SOT-23,
MSOP
16-bit nanoDAC, 4 LSB INL, SOT-23
14-/16-bit nanoDAC, 1 LSB INL,
SOT-23
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
OUT
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
nanoDAC, Quad,
V
V
REF
REF
V
DAC A
DAC B
DAC C
DAC D
DAC A
DAC B
DAC C
DAC D
A
C
REFIN
V
V
REF
REF
B
D
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
www.analog.com
POWER-DOWN
POWER-DOWN
LOGIC
LOGIC
GND
GND
V
V
V
V
V
V
V
V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
A
B
C
D
A
B
C
D

Related parts for AD5024BRUZ

AD5024BRUZ Summary of contents

Page 1

FEATURES Low power quad 12-/14-/16-bit DAC, ±1 LSB INL Pin compatible and performance upgrade to Individual and common voltage reference pin options Rail-to-rail operation 4 5.5 V power supply Power-on reset to zero scale or midscale 3 power-down ...

Page 2

AD5024/AD5044/AD5064 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagrams............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 AC Characteristics........................................................................ 4 Timing Characteristics ................................................................ 5 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. ...

Page 3

SPECIFICATIONS kΩ to GND unless otherwise noted. MAX Table 2. Parameter Min 3 STATIC PERFORMANCE Resolution Relative Accuracy (INL) 4 Differential ...

Page 4

AD5024/AD5044/AD5064 Parameter Min 9 LOGIC OUTPUTS (SDO) Output Low Voltage Output High Voltage − High Impedance Leakage Current High Impedance Output 6 Capacitance POWER REQUIREMENTS V 4 Normal Mode ...

Page 5

TIMING CHARACTERISTICS All input signals are specified with Figure 4 5.5 V. All specifications T DD Table 4. 1 Parameter SCLK Cycle Time SCLK High Time SCLK Low Time SYNC to ...

Page 6

AD5024/AD5044/AD5064 SCLK t 8 SYNC DIN DB31 1 LDAC 2 LDAC CLR V OUT PDL 1 ASYNCHRONOUS LDAC UPDATE MODE. 2 SYNCHRONOUS LDAC UPDATE MODE. SCLK SYNC DB31 DIN INPUT WORD FOR DAC ...

Page 7

ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 5. Parameter Rating V to GND −0 Digital Input Voltage to GND −0 GND −0 OUT ...

Page 8

AD5024/AD5044/AD5064 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 LDAC LDAC can be operated in two modes, asynchronously and synchronously, as shown in this pin low allows any or all DAC registers to ...

Page 9

Table 7. Pin Function Descriptions Pin No. Mnemonic Description 1 LDAC LDAC can be operated in two modes, asynchronously and synchronously, as shown in this pin low allows any or all DAC registers to be updated if the input registers ...

Page 10

AD5024/AD5044/AD5064 TYPICAL PERFORMANCE CHARACTERISTICS 1 4.096V REF 0 25°C A 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 512 16,640 32,768 DAC CODE Figure 8. AD5064/AD5064-1 INL 1 ...

Page 11

4.096V REF 0. 25°C A 0.10 0.05 0 –0.05 –0.10 –0.15 –0.20 512 16,640 32,768 48,896 DAC CODE Figure 14. Total Unadjusted Error (TUE) 1 25°C A 1.4 1.2 ...

Page 12

AD5024/AD5044/AD5064 0 4.096V REF T = 25°C A 0.1 GAIN ERROR 0 FULL-SCALE ERROR –0.1 –0.2 4.50 4.75 5.00 V (V) DD Figure 20. Gain Error and Full-Scale Error vs. Supply Voltage 0. 4.096V REF T ...

Page 13

4.096 REF T = 25° DIGITAL INPUT VOLTAGE (V) Figure 26. Supply Current vs. Digital Input Voltage 5.0 4.5 4.0 3.5 V ...

Page 14

AD5024/AD5044/AD5064 5V 4.096V DD REF 25º –1 –2 –3 –4 0 2.5 5.0 TIME (μs) Figure 32. Analog Crosstalk ...

Page 15

– 3dB POINT –60 10 100 1000 FREQUENCY (kHz) Figure 38. Multiplying Bandwidth 5.0 4.5 4.0 3 25°C ...

Page 16

AD5024/AD5044/AD5064 V = 5V,V = 4.096V DD REF T = 25°C A CH1 20mV CH2 5V M4µs T 8.6% Figure 44. Glitch Upon Exiting Power-Down (1 kΩ to GND) to Zero Scale, No Load DAC A 129mV p-p SCLK A ...

Page 17

TERMINOLOGY Relative Accuracy (INL) For the DAC, relative accuracy, or integral nonlinearity (INL measure of the maximum deviation in LSBs from a straight line passing through the endpoints of the DAC transfer function. Figure 8, Figure 9, and ...

Page 18

AD5024/AD5044/AD5064 DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk measured by ...

Page 19

THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER The AD5024/AD5044/AD5064/AD5064-1 are single 12-/14-/ 16-bit, serial input, voltage output DACs with an individual reference pin. The AD5064-1 model (see the Ordering Guide 16-bit, serial input, voltage output DAC that is identical to ...

Page 20

AD5024/AD5044/AD5064 DB31 (MSB COMMAND BITS ADDRESS BITS DB31 (MSB COMMAND BITS ADDRESS BITS DB31 (MSB ...

Page 21

MODES OF OPERATION There are three main modes of operation: standalone mode where a single device is used, daisy-chain mode for a system that contains several DACs, and power-down mode when the supply current falls to 0.4 μ ...

Page 22

AD5024/AD5044/AD5064 POWER-ON RESET The AD5024/AD5044/AD5064/AD5064-1 contain a power-on reset circuit that initializes the registers to their default values and controls the output voltage during power-up. By connecting the POR pin low, the AD5024/AD5044/AD5064/AD5064-1 output powers up to zero scale. Note ...

Page 23

CLEAR CODE REGISTER The AD5024/AD5044/AD5064/AD5064-1 have a hardware CLR pin that is an asynchronous clear input. The CLR input is falling edge sensitive. Bringing the CLR line low clears the contents of the input register and the DAC registers to ...

Page 24

AD5024/AD5044/AD5064 POWER SUPPLY BYPASSING AND GROUNDING When accuracy is important in a circuit helpful to carefully consider the power supply and ground return layout on the board. The printed circuit board (PCB) containing the AD5024/AD5044/ AD5064/AD5064-1 should have ...

Page 25

MICROPROCESSOR INTERFACING AD5024/AD5044/AD5064/AD5064-1 to Blackfin ADSP- BF53x Interface Figure 52 shows a serial interface between the AD5024/AD5044/ AD5064/AD5064-1 and the Blackfin® ADSP-BF53x microproces- sor. The ADSP-BF53x processor family incorporates two dual- channel synchronous serial ports, SPORT1 and SPORT0, for serial ...

Page 26

AD5024/AD5044/AD5064 APPLICATIONS INFORMATION USING A REFERENCE AS A POWER SUPPLY Because the supply current required by the AD5024/AD5044/ AD5064/AD5064-1 is extremely low, an alternative option is to use a voltage reference to supply the required voltage to the parts (see ...

Page 27

OUTLINE DIMENSIONS 4.50 4.40 4.30 PIN 1 1.05 1.00 0.80 0.15 0.05 COPLANARITY 0.10 0.15 0.05 5.10 5.00 4. 6.40 BSC 1 7 0.65 BSC 1.20 0.20 MAX 0.09 8° SEATING 0° 0.30 PLANE 0.19 COMPLIANT TO JEDEC ...

Page 28

... AD5044BRUZ −40°C to +125°C AD5044BRUZ-REEL7 −40°C to +125°C AD5024BRUZ −40°C to +125°C AD5024BRUZ-REEL7 −40°C to +125°C EVAL-AD5064-1EBZ EVAL-AD5064EBZ RoHS Compliant Part. ©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...

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