AD5024BRUZ Analog Devices Inc, AD5024BRUZ Datasheet - Page 25

• Manufacturer Part Number: AD5024BRUZ
• Description: IC DAC QUAD 12BIT 1LSB 16-TSSOP
• Manufacturer: Analog Devices Inc
• Series: nanoDAC™r

Specifications of AD5024BRUZ

• Data Interface: SPI™
• Settling Time: 8µs
• Number Of Bits: 12
• Number Of Converters: 4
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 30mW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resolution (bits): 12bit
• Sampling Rate: 125kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 4.5V To 5.5V
• Supply Current: 4mA
• Digital Ic Case Style: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MICROPROCESSOR INTERFACING
AD5024/AD5044/AD5064/AD5064-1 to Blackfin ADSP-
BF53x Interface
Figure 52 shows a serial interface between the AD5024/AD5044/
AD5064/AD5064-1 and the
sor. The ADSP-BF53x processor family incorporates two dual-
channel synchronous serial ports, SPORT1 and SPORT0, for
serial and multiprocessor communications. Using SPORT0 to
connect to the AD5024/AD5044/AD5064/AD5064-1, the setup
for the interface is as follows: DT0PRI drives the DIN pin of the
AD5024/AD5044/AD5064/AD5064-1, and TSCLK0 drives the
SCLK of the parts. The SYNC pin is driven from TFS0.
AD5024/AD5044/AD5064/AD5064-1 to 68HC11/68L11
Interface
Figure 53 shows a serial interface between the AD5024/AD5044/
AD5064/AD5064-1 and the 68HC11/68L11 microcontroller.
SCK of the 68HC11/68L11 drives the SCLK of the AD5024/
AD5044/AD5064/AD5064-1, and the MOSI output drives the
serial data line of the DAC.
The SYNC signal is derived from a port line (PC7). The setup
conditions for correct operation of this interface are as follows:
The 68HC11/68L11 is configured with its CPOL bit as 0, and its
CPHA bit as 1. When data is being transmitted to the DAC, the
SYNC line is taken low (PC7). When the 68HC11/68L11 is
configured as described previously, data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11/68L11 is transmitted in 8-bit bytes with only eight
falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. To load data to the AD5024/AD5044/
AD5064, PC7 is left low after the first eight bits are transferred,
and a second serial write operation is performed to the DAC.
PC7 is taken high at the end of this procedure.
Figure 53. AD5024/AD5044/AD5064/AD5064-1 to 68HC11/68L11 Interface
Figure 52. AD5024/AD5044/AD5064/AD5064-1 to Blackfin ADSP-BF53x
*ADDITIONAL PINS OMITTED FOR CLARITY.
*ADDITIONAL PINS OMITTED FOR CLARITY.
68HC11/68L11*
ADSP-BF53x*
TSCLK0
DT0PRI
MOSI
TFS0
SCK
PC7
Blackfin®
Interface
SYNC
DIN
SCLK
SYNC
SCLK
DIN
ADSP-BF53x microproces-
AD5064-1
AD5064-1
AD5024/
AD5044/
AD5064/
AD5024/
AD5044/
AD5064/
*
*
Rev. D | Page 25 of 28
AD5024/AD5044/AD5064/AD5064-1 to 80C51/80L51
Interface
Figure 54 shows a serial interface between the AD5024/AD5044/
AD5064/AD5064-1 and the 80C51/80L51 microcontroller. The
setup for the interface is as follows: TxD of the 80C51/80L51
drives SCLK of the AD5024/AD5044/AD5064/AD5064-1, and
RxD drives the serial data line of the part. The SYNC signal is
again derived from a bit-programmable pin on the port. In this
case, Port Line P3.3 is used. When data is to be transmitted to the
AD5024/AD5044/AD5064/AD5064-1, P3.3 is taken low. The
80C51/80L51 transmit data in 8-bit bytes only; thus, only eight
falling clock edges occur in the transmit cycle. To load data to
the DAC, P3.3 is left low after the first eight bits are transmitted,
and a second write cycle is initiated to transmit the second byte of
data. P3.3 is taken high following the completion of this cycle.
The 80C51/80L51 output the serial data in a format that has the
LSB first. The AD5024/AD5044/AD5064/AD5064-1 must
receive data with the MSB first. The 80C51/80L51 transmit
routine should take this into account.
AD5024/AD5044/AD5064/AD5064-1 to MICROWIRE
Interface
Figure 55 shows an interface between the AD5024/AD5044/
AD5064/AD5064-1 and any MICROWIRE-compatible device.
Serial data is shifted out on the falling edge of the serial clock and is
clocked into the AD5024/AD5044/AD5064/AD5064-1 on the
rising edge of the SCLK.
Figure 54. AD5024/AD5044/AD5064/AD5064-1 to 80C512/80L51 Interface
Figure 55. AD5024/AD5044/AD5064/AD5064-1 to MICROWIRE Interface
*ADDITIONAL PINS OMITTED FOR CLARITY.
*ADDITIONAL PINS OMITTED FOR CLARITY.
80C51/80L51*
MICROWIRE*
P3.3
RxD
TxD
SO
CS
SK
AD5024/AD5044/AD5064
SYNC
SCLK
DIN
SYNC
DIN
SCLK
AD5064-1
AD5064-1
AD5024/
AD5044/
AD5064/
AD5024/
AD5044/
AD5064/
*
*