AD5024BRUZ Analog Devices Inc, AD5024BRUZ Datasheet - Page 5

• Manufacturer Part Number: AD5024BRUZ
• Description: IC DAC QUAD 12BIT 1LSB 16-TSSOP
• Manufacturer: Analog Devices Inc
• Series: nanoDAC™r

Specifications of AD5024BRUZ

• Data Interface: SPI™
• Settling Time: 8µs
• Number Of Bits: 12
• Number Of Converters: 4
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 30mW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resolution (bits): 12bit
• Sampling Rate: 125kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 4.5V To 5.5V
• Supply Current: 4mA
• Digital Ic Case Style: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING CHARACTERISTICS
All input signals are specified with t
Figure 5. V
Table 4.
Parameter
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge Setup Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time (Single Channel Update)
Minimum SYNC High Time (All Channel Update)
SYNC Rising Edge to SCLK Fall Ignore
LDAC Pulse Width Low
SCLK Falling Edge to LDAC Rising Edge
CLR Minimum Pulse Width Low
SCLK Falling Edge to LDAC Falling Edge
CLR Pulse Activation Time
SCLK Rising Edge to SDO Valid
SCLK Falling Edge to SYNC Rising Edge
SYNC Rising Edge to SCLK Rising Edge
SYNC Rising Edge to LDAC/CLR/PDL Falling Edge (Single Channel Update)
SYNC Rising Edge to LDAC/CLR/PDL Falling Edge (All Channel Update)
PDL Minimum Pulse Width Low
Power-up Time
1
2
3
4
Circuit and Timing Diagrams
Maximum SCLK frequency is 50 MHz at V
Daisy-chain mode only.
Measured with the load circuit of Figure 3. t
Time to exit power-down mode to normal mode of AD5024/AD5044/AD5064/AD5064-1, 32
DD
1
= 4.5 V to 5.5 V. All specifications T
4
DD
R
= 4.5 V to 5.5 V. Guaranteed by design and characterization; not production tested.
15
= t
determines the maximum SCLK frequency in daisy-chain mode. AD5064-1 only.
F
Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications
= 1 ns/V (10% to 90% of V
TO OUTPUT
MIN
PIN
to T
50pF
C
L
MAX
2mA
2mA
, unless otherwise noted.
Rev. D | Page 5 of 28
I
I
OL
OH
DD
) and timed from a voltage level of (V
nd
V
OH
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
clock edge to 90% of DAC midscale value, with output unloaded.
1
2
3
4
5
6
7
8
8
9
10
11
12
13
14
15
16
17
18
18
19
2
2
2
2
(MIN) + V
2, 3
2
OL
(MAX)
Min
20
10
10
17
5
5
5
3
8
17
20
20
10
10
10.6
5
8
2
8
20
4.5
AD5024/AD5044/AD5064
Typ
IL
+ V
IH
)/2. See Figure 4 and
Max
30
22
Unit
ns
ns
ns
ns
ns
ns
ns
μs
μs
ns
ns
ns
ns
ns
μs
ns
ns
ns
μs
μs
ns
μs