AD5551BRZ Analog Devices Inc, AD5551BRZ Datasheet - Page 4

• Manufacturer Part Number: AD5551BRZ
• Description: IC DAC 14BIT SERIAL-IN 8-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD5551BRZ

• Data Interface: Serial
• Settling Time: 1µs
• Number Of Bits: 14
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 6.05mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Resolution (bits): 14bit
• Sampling Rate: 1MSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 2.7V To 5.5V
• Supply Current: 300µA
• Digital Ic Case Style: SOIC
• Number Of Channels: 1
• Resolution: 14b
• Interface Type: Serial (3-Wire, SPI, QSPI, Microwire)
• Single Supply Voltage (typ): 3/5V
• Dual Supply Voltage (typ): Not RequiredV
• Architecture: R-2R
• Power Supply Requirement: Single
• Output Type: Voltage
• Integral Nonlinearity Error: ±1LSB
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: SOIC N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD5551/AD5552
TIMING CHARACTERISTICS
V
Table 2.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
1
2
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
Guaranteed by design, not production tested.
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns (10% to
90% of +3 V and timed from a voltage level of +1.6 V).
DD
= 2.7 V to 5.5 V, 2.5 V ≤ V
1, 2
LDAC*
SCLK
DIN
CS
*AD5552 ONLY. MAY BE TIED PERMANENTLY LOW IF REQUIRED.
Limit at T
All Versions
25
40
20
20
15
15
35
20
15
0
30
30
30
t
12
REF
MIN
t
6
, T
≤ 5.5 V, AGND = DGND = 0 V. All specifications −40°C ≤ T
t
DB13
4
t
MAX
8
t
9
t
2
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Figure 3. Timing Diagram
Rev. A | Page 4 of 16
t
1
t
3
DB0
Description
SCLK cycle frequency
SCLK cycle time
SCLK high time
SCLK low time
CS low to SCLK high setup
CS high to SCLK high setup
SCLK high to CS low hold time
SCLK high to CS high hold time
Data setup time
Data hold time
LDAC pulse width
CS high to LDAC low setup
CS high time between active periods
t
7
t
t
5
11
t
10
A
≤ +85°C, unless otherwise noted.