TS68EN360VA25L E2V, TS68EN360VA25L Datasheet - Page 65

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TS68EN360VA25L

Manufacturer Part Number
TS68EN360VA25L
Description
Manufacturer
E2V
Datasheet

Specifications of TS68EN360VA25L

Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / Rohs Status
Not Compliant
Figure 7-55. Ethernet Receive Timing
Figure 7-56. Ethernet Transmit Timing
Notes:
e2v semiconductors SAS 2008
2. If RENA is deasserted before TENA, or RENA is not asserted at all during transit, then CSL bit is set in the buffer descriptor
1. Transmit clock invert (TCI) bit in GSMR is set.
TENA (RTS1)
RENA (CD1)
RENA (CD1)
(OUTPUT)
(OUTPUT)
at the end of frame transmission.
(NOTE 1)
(NOTE 2)
(INPUT)
(INPUT)
(INPUT)
TCLK1
RCLK1
TXD1
RXD1
128
133
131
121
124
128
129
125
130
132
121
122
123
126
LAST BIT
134
127
0886C–HIREL–04/08
TS68EN360
65

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