S2065A Applied Micro Circuits Corporation, S2065A Datasheet - Page 15

• Manufacturer Part Number: S2065A
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S2065A

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.13V
• Operating Supply Voltage (max): 3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / Rohs Status: Not Compliant

October 13, 2000 / Revision G
8B/10B Decoding
After performing serial-to-parallel conversion, the
S2065 provides 8B/10B decoding of the data. The
received 10-bit codeword is decoded to recover the
original 8-bit data. The decoder also checks for er-
rors and flags, either invalid codeword errors or run-
ning disparity errors by assertion of the ERRx signal.
Error type is determined by examining the EOF out-
put in accordance with Table 8. When more than one
reportable condition occurs simultaneously, reporting
is in accordance with the rank assigned by Table 8.
Data Output
Data is output on the DOUT[0:7] outputs. K-charac-
ters are flagged using the KFLAG signal. The EOF
(with KFLAG) is used to indicate the reception of a
valid K28.5 character. Invalid codewords and decod-
ing errors are indicated on the ERR output. KFLAG,
EOF, and ERR are buffered with the data in the
FIFO to ensure that all outputs are synchronized at
the S2065 outputs. Errors are reported indepen-
dently for each channel in both CHANNEL LOCK
mode and NORMAL mode operation.
The S2065 TTL outputs are optimized to drive 65
line impedances. Internal source matching provides
good performance on unterminated lines of reason-
able length.
QUAD SERIAL BACKPLANE DEVICE WITH DUAL I/O
Parallel Output Clock Rate
Two output clock modes are supported. When
CMODE is HIGH, a complementary TTL clock at the
data rate is provided on the RCxP/N outputs. Data
should be clocked on the rising edge of RCxP. When
CMODE is LOW, a complementary TTL clock at 1/2
the data rate is provided. Data should be latched on
the rising edge of RCxP and the rising edge of
RCxN.
The S2065 will operate properly when multiple K28.5
characters are received. Byte alignment is achieved
after the first K28.5 is received. The RCxP/N clock
operates without glitches or loss of cycles.
Table 7. Output Clock Modes
H
F
l l u
a
f l
C
C
M
o l
o l
o
k c
k c
d
e
M
M
o
o
d
d
e
e
C
M
O
0
1
D
E
R
C
x
V
V
C
C
P
N /
O
O
2 /
1 /
S2065
F
0
0
e r
. q
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