TXC-05802AIPQ Transwitch Corporation, TXC-05802AIPQ Datasheet - Page 10

• Manufacturer Part Number: TXC-05802AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-05802AIPQ

• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature Classification: Industrial
• Package Type: PQFP
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / Rohs Status: Not Compliant

H: CRC-4 field. This 4-bit field (H3-H0) provides Routing Header error protection across the CellBus bus in both
Tandem Routing Header Format
The two-byte Tandem Routing Header format in Bits 15-0 of Cycle 1 is the same as the CellBus Bus Routing
Header format, if it is to be used by a cascaded CellBus bus, or may conform to a different specification if it is
used by another system. The Tandem Routing Header is passed unchanged through the CellBus bus.
CellBus Bus Status Signals and Monitoring
The CUBIT- Pro provides the capability to monitor the activity on the CellBus bus. The essential signals that
determine whether the bus is active (in the absence of any cell traffic) are the clock signals and the frame
pulse.
The CellBus bus clocks (read and write) are generated externally to the CUBIT- Pro . If either of these clocks
fails, the entire bus will cease operation. The CUBIT- Pro provides the capability to detect the absence of clock
signal for more than the equivalent of 32 processor clock (PCLK) cycles. The failure detection is performed
independently for the CellBus Bus Read Clock (CBRC) and the CellBus Bus Write Clock (CBWC).
Two bits (register 05H bits CBLORC and CBLOWC) in the CUBIT- Pro memory map are used to indicate the
clock loss event. Once the event is detected, these bits in register 05H will remain set to one until the micropro-
cessor reads the register, at which point the register will be cleared. These events can be used to generate a
microprocessor interrupt provided that the appropriate bits in the interrupt enable register (address 06H, bits
INTENA1 and INTENA0) are 1.
The second monitoring function concerns the detection of loss of frame. The detection mechanism looks for
two consecutive missing CellBus bus frame pulses in 32-user mode (U32 = Low), and four consecutive missing
CellBus bus frame pulses in 16-user mode. The CellBus Bus Read Clock must be present to detect Loss of
Frame Pulse. If CellBus Bus Read Clock is present and CellBus Bus Write Clock is not, then both CBLOWC and
CBLOF will be set. CBLOF can generate an interrupt to the microprocessor assuming that the appropriate
interrupt enable bit is 1 (register 06H, bit 2: INTENA2).
directions. It is calculated over the 12-bit word (X11-X0) in bits 31-20 of the Routing Header using the fol-
lowing logic:
where
cally calculates the corresponding CRC-4 and sets to 1 the status bit CRCF (bit 7 in register 08H) if it is not
the same as that in bits H3-H0 of the received Routing Header. This status bit may be enabled to cause an
interrupt signal to the microprocessor by setting to 1 the enable bit INTEN7 (bit 7 in register 09H). For cells
supplied to the cell inlet interface from an external source for transmission via the CellBus bus, the CRC-4
may either be supplied in the input signal by use of external logic (as is required for the CUBIT device) or it
may be generated internally and inserted into the Routing Header by the CUBIT- Pro . Setting control bit
CRC4EN to 1 (bit 3 in register 0EH) activates the internal CRC-4 insertion for all incoming cells (i.e., not
only data cells, but also control cells and loopback cells). When control bit CRC4I (bit 4 in register 0EH) is
set to 1 the internally generated CRC-4 is inverted for testing purposes. This bit has no effect on an exter-
nally-supplied CRC-4. For operation in the CUBIT TXC-05801 mode with an externally-supplied CRC-4, bit
CRC4EN should be set to 0, which is the default at power-up/reset.
represents logical exclusive-or. For cells arriving from the CellBus bus, the CUBIT- Pro automati-
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Ed. 3, November 1999
TXC-05802
CUBIT- Pro
TXC-05802-MB