TXC-05802AIPQ Transwitch Corporation, TXC-05802AIPQ Datasheet - Page 46

• Manufacturer Part Number: TXC-05802AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-05802AIPQ

• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature Classification: Industrial
• Package Type: PQFP
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / Rohs Status: Not Compliant

MICROPROCESSOR PORT
TRANSLATION RAM ACCESS PORT
RDY/DTACK
TRA(17-16)
TRA(15-12)
TRA(11-8)
TRD (7-4)
TRD (3-0)
TRA(7-4)
TRA(3-0)
INT/IRQ
Symbol
Symbol
RD/WR
MOTO
D(7-6)
D(5-2)
D(1-0)
TRWE
A(7-6)
A(5-4)
A(3-0)
TROE
PCLK
RD or
SEL
WR
150, 152,
160-163,
165-168,
170-173,
140-143,
175-178
145-148
Pin No.
Pin No.
10, 11,
13, 14,
21, 22,
24-27,
29, 30
16-19
136
138
38
40
32
36
39
34
35
I/O/P
I/O/P
OD
I/O
I/O
O
O
O
O
I
I
I
I
I
I
TTL 8 mA
TTL 4 mA Interrupt: Active high for Intel, active low for Motorola.
TTL 4 mA Translation RAM Address Bus: 18-bit address output for
TTL 4 mA
TTL 4 mA Translation RAM Output Enable: Active low output
TTL 4 mA Translation RAM Write Enable: Active low write enable.
TTL 6 mA Ready or Data Transfer Acknowledge: Active high
Type
Type
TTL/
TTL/
TTL
TTL
TTL
TTL
TTL
TTL
Address Bus: 8-bit address lines from microprocessor,
used to address CUBIT- Pro register memory. A0 is LSB.
High is logic 1.
Data Bus: Bidirectional 8-bit data lines used for transfer-
ring data to and from microprocessor. D0 is LSB. High is
logic 1.
Motorola Mode: Select Motorola operation if high, Intel if
low.
Processor Clock: Rising edge used for data transfer.
Read/Write: Data transfer command for CUBIT- Pro mem-
ory. Read (low) for Intel. Read (high) / Write (low) for
Motorola.
Ready for Intel, active low Data Transfer Acknowledge for
Motorola. This output is an open-drain buffer which
requires an external pull-up resistor.
Select: Active low signal to enable data transfer.
Write: Active low write command for transferring data to
CUBIT- Pro memory in Intel mode. This input must be held
high in Motorola mode.
up to 256k byte Translation RAM. TRA(7-0) are cell data
outlet 8 LSB if ABRENA is enabled. TRA0 is LSB. High is
logic 1.
Translation RAM Data Bus: Bidirectional 8-bit data bus.
TRD(7-0) are cell data inlet 8 LSB if ABRENA is enabled.
TRD0 is LSB. High is logic 1.
enable.
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Name/Function
Name/Function
Ed. 3, November 1999
TXC-05802
CUBIT- Pro
TXC-05802-MB