TXC-05802AIPQ Transwitch Corporation, TXC-05802AIPQ Datasheet - Page 24

• Manufacturer Part Number: TXC-05802AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-05802AIPQ

• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature Classification: Industrial
• Package Type: PQFP
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / Rohs Status: Not Compliant

CUBIT- Pro
TXC-05802
Translation RAM Organization
The translation RAM partitioning is shown in Figure 18. The lower portion of the TRAM contains the translation
records for VPIs. When the UNI mode is enabled (control bit UNI=1), the number of VPI entries is 256. When
NNI mode is enabled (UNI=0), 4096 VPI entries are present.
Depending on whether the Tandem Routing Header is enabled the VP Record has: four bytes if the Tandem
Routing Header (TRH) is not used (control bit TRHENA=0), and six bytes if the TRH is used (TRHENA=1). The
size of the VPI memory space in this mode ranges from 1024 bytes (UNI mode, no TRH, 4 x 256) to 24576
bytes (NNI and TRH, 6 x 4096).
The memory space above the VPI section is the VCI translation record storage space, divided into a number of
VCI pages. Each VCI page contains the translation records for 128, 256, 512, or 1024 VCIs.
Depending on whether Tandem Routing Header is enabled the VC Record has: six bytes if the Tandem Rout-
ing Header (TRH) is not used (control bit TRHENA=0), and eight bytes if the TRH is used (TRHENA=1).
The number of VCI records per page (VRP) depends on the settings of the VRPS[1,0] control bits in register
0EH as follows:
VRPS[1,0]=0,0: VRP is 256
VRPS[1,0]=0,1: VRP is 512
VRPS[1,0]=1,0: VRP is 1024
VRPS[1,0]=1,1: VRP is 128
The total size of the TRAM which the CUBIT- Pro can support is up to 262,144 bytes (256k). Hence, the num-
ber of VCI translation table pages which can be supported is a function of memory size, and the states of con-
trol bits UNI and TRHENA. For example, the maximum number (M) of VCI memory pages, for maximum
memory size, is as follows:
VRPS[1,0]=0,0: VRP is 256
if UNI=1, TRHENA = 1; M = (262144-(256*6))/(256*8) = 127 VCI Pages,
if UNI=1, TRHENA = 0; M = (262144-(256*4))/(256*6) = 170 VCI Pages.
VRPS[1,0]=0,1: VRP is 512
if UNI=1, TRHENA = 1; M = (262144-(256*6))/(512*8) = 63 VCI Pages,
if UNI=1, TRHENA = 0; M = (262144-(256*4))/(512*6) = 85 VCI Pages.
VRPS[1,0]=1,0: VRP is 1024
if UNI=1, TRHENA = 1; M = (262144-(256*6))/(1024*8) = 31 VCI Pages,
if UNI=1, TRHENA = 0; M = (262144-(256*4))/(1024*6) = 42 VCI Pages.
VRPS[1,0]=1,1: VRP is 128
if UNI=1, TRHENA = 1; M = (262144-(256*6))/(128*8) = 254 VCI Pages,
if UNI=1, TRHENA = 0; M = Min[(262144-(256*4))/(128*6), 256] = Min [340,256] = 256 VCI Pages.
if VRPS[1,0]=1,1, VRP is 128. The maximum number of addressable pages is 256, even though, theoretically,
340 pages could fit in a SRAM of 256k bytes.
TXC-05802-MB
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Ed. 3, November 1999