RD1950MPXM2010GS Freescale Semiconductor, RD1950MPXM2010GS Datasheet - Page 47

• Manufacturer Part Number: RD1950MPXM2010GS
• Manufacturer: Freescale Semiconductor

Specifications of RD1950MPXM2010GS

• Lead Free Status / Rohs Status: Compliant

3.7.2 ADC Data Register
One 8-bit result register is provided. This register is updated each time an ADC conversion completes.
3.7.3 ADC Input Clock Register
This register selects the clock frequency for the ADC.
ADIV2–ADIV0 — ADC Clock Prescaler Bits
Freescale Semiconductor
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate
the internal ADC clock.
should be set between f
entire conversion time (maximum = 17 ADC clock cycles).
Address: $003E
Address: $003F
Reset:
Reset:
Read:
Read:
Write:
Write:
ADIV2
Bit 7
AD7
Bit 7
0
X = don’t care
ADIV2
Table 3-2
Figure 3-5. ADC Input Clock Register (ADICLK)
ADIC(MIN)
0
0
0
0
1
= Unimplemented
= Unimplemented
ADIV1
Figure 3-4. ADC Data Register (ADR)
MC68HC908QY/QT Family Data Sheet, Rev. 6
AD6
6
6
0
Table 3-2. ADC Clock Divide Ratio
and f
shows the available clock configurations. The ADC clock frequency
ADIV1
X
0
0
1
1
ADIV0
ADIC(MAX)
AD5
5
5
0
Indeterminate after reset
ADIV0
AD4
. The analog input level should remain stable for the
X
0
1
0
1
4
4
0
0
AD3
3
3
0
0
ADC Clock Rate
Bus clock ÷ 16
Bus clock ÷ 1
Bus clock ÷ 2
Bus clock ÷ 4
Bus clock ÷ 8
AD2
2
2
0
0
AD1
1
1
0
0
Input/Output Registers
Bit 0
AD0
Bit 0
0
0
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