82V2608BB IDT, Integrated Device Technology Inc, 82V2608BB Datasheet - Page 97

• Manufacturer Part Number: 82V2608BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2608BB

• Utopia Level: Level 2
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Package Type: BGA
• Pin Count: 208
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

O
OCD_TC ...................................................................................... 61
OIF-IMA ....................................................................................... 61
OUTPUT_FIFO_DATA_REG register ................................................ 25
OUTPUT_FIFO_INTERNAL_STATE_REG register .......................... 26
OUTPUT_FIFO_LENGTH_REG register ........................................... 25
P
performance monitoring ..................................................................... 71
physical and electrical characteristics ................................................ 81
pin description
PMON ................................................................................................. 71
PMON parameters
power supplies and grounds .............................................................. 16
R
recover links ....................................................................................... 70
RecoverLink command ................................................................ 54
register
register description ............................................................................. 25
register list and map ........................................................................... 24
restart a group .................................................................................... 70
IDT82V2608
Index
global signals .............................................................................. 12
JTAG & Scan interface ............................................................... 16
line interface ............................................................................... 13
microprocessor interface ............................................................ 14
others ......................................................................................... 17
power supplies and grounds ....................................................... 16
SRAM interface .......................................................................... 15
GR-UAS-IMA .............................................................................. 71
HCS_ERR_TC ..................................................................... 61
IV-IMA ................................................................................. 61
OCD_TC .............................................................................. 61
OIF-IMA ............................................................................... 61
Rx-Stuff-IMA ........................................................................ 61
Rx-UUS-IMA ........................................................................ 61
Rx-UUS-IMA-FE .................................................................. 61
SES-IMA .............................................................................. 61
SES-IMA-FE ........................................................................ 61
Tx-Stuff-IMA ........................................................................ 61
Tx-UUS-IMA ........................................................................ 61
Tx-UUS-IMA-FE .................................................................. 61
UAS-IMA .............................................................................. 61
UAS-IMA-FE ........................................................................ 61
FIFO_INT_ENABLE_REG .......................................................... 26
FIFO_INT_RESET_REG ............................................................ 26
FIFO_STATE_REG .................................................................... 26
INPUT_FIFO_DATA_REG ......................................................... 25
INPUT_FIFO_INTERNAL_STATE_REG ................................... 27
INPUT_FIFO_LENGTH_REG .................................................... 25
OUTPUT_FIFO_DATA_REG ..................................................... 25
OUTPUT_FIFO_INTERNAL_STATE_REG ............................... 26
OUTPUT_FIFO_LENGTH_REG ................................................ 25
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RestartGrp command ...................................................................52
RFI-IMA .............................................................................................. 72
Rx-Stuff-IMA ................................................................................61
Rx-Unusable-FE ................................................................................ 72
Rx-UUS-IMA ................................................................................61
Rx-UUS-IMA-FE ..........................................................................61
S
SES-IMA ......................................................................................61
SES-IMA-FE ................................................................................61
slave side ........................................................................................... 73
spaced mapping ................................................................................. 21
SRAM interface ............................................................................15
SRAM interface timing ....................................................................... 89
SRAM size
start up a group .................................................................................. 70
StartGroup command ...................................................................48
StartLASR command ...................................................................49
StartTestPattern command ................................................................ 66
Start-up-FE ........................................................................................ 72
StopTestPattern command ................................................................ 68
stuffing mode ..................................................................................... 30
T
T1 ISDN mode ................................................................................... 22
T1 normal mode ................................................................................. 22
timing
timing clock mode
timing reference link ........................................................................... 30
TRL .................................................................................................... 30
Tx-Stuff-IMA .................................................................................61
Tx-Unusable-FE ................................................................................. 72
Tx-UUS-IMA .................................................................................61
Tx-UUS-IMA-FE ...........................................................................61
U
UAS-IMA ......................................................................................61
UAS-IMA-FE ................................................................................61
UNI mode ........................................................................................... 30
Utopia interface .................................................................................. 18
Utopia interface timing ....................................................................... 83
Utopia loopback ................................................................................. 18
maximum delay tolerance .......................................................... 29
CTC ............................................................................................ 30
ITC ............................................................................................. 30
line interface timing .................................................................... 84
microprocessor interface timing
SRAM interface timing ............................................................... 89
Utopia interface timing ............................................................... 83
line interface ............................................................................... 23
Intel .................................................................................... 87
Motorola ............................................................................. 85
Inverse Multiplexing for ATM
December 4, 2006
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