PEB20570FV3.1T Infineon Technologies, PEB20570FV3.1T Datasheet - Page 131

• Manufacturer Part Number: PEB20570FV3.1T
• Manufacturer: Infineon Technologies

Specifications of PEB20570FV3.1T

• Lead Free Status / Rohs Status: Not Compliant

The HDLC automatically recognizes HDLC frames with the following interframe time fill
combinations:
• n consecutive flags (n = 1, 2, 3,.. ; n = 1 is called shared flag, if the closing flag of one
• m "ones" between the closing flag and the opening flag (even when m = 1 to 5)
• corrupted flag between the closing flag and the opening flag
The HDLCU may process up to 32 full-duplex HDLC channels in parallel. As it is
controlled by the DSP, it is very flexible. The HDLCU includes 32 Receive Input Buffers,
32 Receive Output Buffers, 32 Transmit Input Buffers and 32 Transmit Output Buffers,
some HDLC protocol processing logic and a command RAM.
Figure 44
Figure 44
is 1 Byte small, hence one byte is assigned to each HDLC channel per direction. The
Transmit Output Buffer is 2 Bytes as it also contains a 7-bit status vector assigned to the
channel.
Data Sheet
Receive Output Buffer
frame is the opening flag of the next frame. n > 1 is also called unshared flag mode.)
Receive Input Buffer
32 channels
encoded
decoded
32 channels
DSP data double buffer
shows the HDLCU structure. Each buffer, except the Transmit Output Buffer,
HDLCU General Block Diagram
DSP D-Buffer*
Processing
Internal
32x8
32x8
DSP Control
command
32x8
RAM
114
Processing
32x16
Internal
DSP D-Buffer*
32x8
DSP Data Double Buffer
Transmit Output Buffer
Transmit Input Buffer
Functional Description
32 channels
32 channels
* Frame-buffers of the IOMU,
PCMU or IOM-2000 that belong to
the DSP during the present frame
PEB 20570
PEB 20571
2003-07-31