DAC1405D650HW/C1,5 NXP Semiconductors, DAC1405D650HW/C1,5 Datasheet - Page 23

• Manufacturer Part Number: DAC1405D650HW/C1,5
• Description: IC DAC 14BIT 650MSPD DL 100HTQFP
• Manufacturer: NXP Semiconductors

Specifications of DAC1405D650HW/C1,5

• Settling Time: 20ns
• Number Of Bits: 14
• Data Interface: SPI™
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 1.4W
• Operating Temperature: -45°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935286775518

NXP Semiconductors
DAC1405D650
Product data sheet
In the Interleaved mode, both DACs use the same data input at twice the Dual-port mode
frequency. Data enters the latch on the rising edge of the internal clock signal. The data is
sent to either latch I or latch Q, depending on the SELIQ signal.
The SELIQ input (pin 41) allows the synchronization of the internally de-multiplexed I and
Q channels; see
edge)”.
SELIQ can be either a synchronous or asynchronous (single rising edge, single pulse)
signal. The first data following the SELIQ rising edge will be sent in channel I and following
data will be sent in channel Q. After this, data will be distributed alternately between these
channels.
Fig 6.
Fig 7.
(asynchronous alternative 1)
(asynchronous alternative 2)
Interleaved mode operation
Interleaved mode timing (8x interpolation, latch on rising edge)
(synchronous alternative)
Qn/SELIQ
All information provided in this document is subject to legal disclaimers.
In
Figure 7 “Interleaved mode timing (8x interpolation, latch on rising
Latch Q output
Latch I output
Rev. 3 — 10 September 2010
CLK
SELIQ
SELIQ
SELIQ
Dual 14-bit DAC, up to 650 Msps; 2×, 4× and 8× interpolating
dig
In
LATCH
LATCH
Q
I
N
N + 1
2 ×
2 ×
XX
XX
FIR 1
FIR 1
N + 2
2 ×
2 ×
FIR 2
FIR 2
N + 3
N + 1
N
DAC1405D650
N + 4
2 ×
2 ×
FIR 3
FIR 3
© NXP B.V. 2010. All rights reserved.
N + 5
N + 2
N + 3
001aaj586
001aaj814
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