DAC1405D650HW/C1,5 NXP Semiconductors, DAC1405D650HW/C1,5 Datasheet - Page 25

• Manufacturer Part Number: DAC1405D650HW/C1,5
• Description: IC DAC 14BIT 650MSPD DL 100HTQFP
• Manufacturer: NXP Semiconductors

Specifications of DAC1405D650HW/C1,5

• Settling Time: 20ns
• Number Of Bits: 14
• Data Interface: SPI™
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 1.4W
• Operating Temperature: -45°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935286775518

NXP Semiconductors
DAC1405D650
Product data sheet
10.5 Timing
The DAC1405D650 can operate at an update rate (f
data rate (f
diagram”.
The typical performances are measured at 50 % duty cycle but any timing within the limits
of the characteristics will not alter the performance.
In
The setting applied to PLL_DIV[1:0] (register 02h[4:3]; see
map”) allows the frequency between the digital part and the DAC core to be adjusted.
Table 31.
The settings applied to PLL_PHASE[1:0] (register 02h[2:1]) and PLL_POL
(register 02h[0]), allows adjustment of the phase and polarity of the sampling clock. This
occurs at the input of the DAC core and depends mainly on the sampling frequency. Some
examples are given in
Table 32.
Mode
Dual Port
Dual Port
Dual Port
Interleaved
Interleaved
Interleaved
Mode
Dual Port
Dual Port
Dual Port
Interleaved
Interleaved
Interleaved
Fig 10. Input timing diagram
Table 31
(CLKP-CLKN)
data
Frequencies
Sample clock phase and polarity examples
“Frequencies”, the links between internal and external clocking are defined.
In/Qn
CLK
) of up to 160 MHz. The input timing is shown in
All information provided in this document is subject to legal disclaimers.
CLK input
(MHz)
160
160
80
320
320
160
Input data rate
(MHz)
80
80
80
160
160
160
Rev. 3 — 10 September 2010
Table 32 “Sample clock phase and polarity
Dual 14-bit DAC, up to 650 Msps; 2×, 4× and 8× interpolating
Input data rate
(MHz)
160
160
80
320
320
160
90 %
t
su(i)
Interpolation
2×
4×
8×
2×
4×
8×
N
50 %
t
h(i)
90 %
Interpolation
2×
4×
8×
2×
4×
8×
Update rate
(Msps)
160
320
640
160
320
640
s
) of up to 650 Msps and with an input
N + 1
t
w(CLK)
DAC1405D650
Table 9 “Register allocation
Update rate
(Msps)
320
640
640
320
640
640
PLL_PHASE
[1:0]
01
01
01
01
01
01
Figure 10 “Input timing
examples”.
N + 2
© NXP B.V. 2010. All rights reserved.
PLL_DIV[1:0]
01 (/4)
01 (/4)
10 (/8)
00 (/2)
00 (/2)
01 (/4)
001aaj815
PLL_POL
1
0
1
1
0
1
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