DS90CR481VJDX/NOPB National Semiconductor, DS90CR481VJDX/NOPB Datasheet - Page 18

• Manufacturer Part Number: DS90CR481VJDX/NOPB
• Manufacturer: National Semiconductor

Specifications of DS90CR481VJDX/NOPB

• Number Of Elements: 8
• Number Of Receivers: 48
• Number Of Drivers: 8
• Input Type: CMOS/TTL
• Operating Supply Voltage (typ): 3.3V
• Output Type: Serializer
• Differential Output Voltage: 450mV
• Transmission Data Rate: 5376Mbps
• Power Dissipation: 2.3W
• Operating Temp Range: -10C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Lead Free Status / Rohs Status: Compliant

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RxINP
RxINM
RxOUT
RxCLKP
RxCLKM
RxCLKOUT
PLLSEL
DESKEW
PD
V
GND
PLLV
PLLGND
LVDSV
LVDSGND
NC
DS90CR482 Pin Descriptions—Channel Link Receiver
Note 11: These receivers have input fail-safe bias circuitry to guarantee a stable receiver output for floating or terminated receiver inputs. Under test conditions
receiver inputs will be in a HIGH state. If the cable interconnect (media) are disconnected which results in floating/terminated inputs, the outputs will remain in the
last valid state.
Note 12: The DS90CR482 is design to automatically detect the DC Balance or non-DC Balance transmitted data from the DS90CR481 and deserialize the LVDS
data according to the define bit mapping.
CC
CC
Pin Name
CC
I/O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
Positive LVDS differential data inputs.
Negative LVDS differential data inputs.
TTL level data outputs. In PowerDown (PD = Low) mode, receiver outputs are
forced to a Low state.
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL level clock output. The rising edge acts as data strobe.
PLL range select. This pin must be tied to V
future use. (Note 10)
Deskew / Oversampling “on/off” select. When using the Deskew / Oversample
feature this pin must be tied to V
(Note 10) Deskew is only supported in the DC Balance mode.
TTL level input. When asserted (low input) the receiver outputs are Low. (Note 10)
Power supply pins for TTL outputs and digital circuitry. Bypass not required on Pins
6 and 77.
Ground pins for TTL outputs and digital circuitry.
Power supply for PLL circuitry.
Ground pin for PLL circuitry.
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
No Connect. Make NO Connection to these pins - leave open.
18
CC
. Tieing this pin to ground disables this feature.
Description
CC
. NC or tied to Ground is reserved for