DS90CR481VJDX/NOPB National Semiconductor, DS90CR481VJDX/NOPB Datasheet - Page 5
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DS90CR481VJDX/NOPB
Manufacturer Part Number
DS90CR481VJDX/NOPB
Description
Manufacturer
National Semiconductor
Datasheet
1.DS90CR481VJDXNOPB.pdf
(21 pages)
Specifications of DS90CR481VJDX/NOPB
Number Of Elements
8
Number Of Receivers
48
Number Of Drivers
8
Input Type
CMOS/TTL
Operating Supply Voltage (typ)
3.3V
Output Type
Serializer
Differential Output Voltage
450mV
Transmission Data Rate
5376Mbps
Power Dissipation
2.3W
Operating Temp Range
-10C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Package Type
TQFP
Lead Free Status / Rohs Status
Compliant
LLHT
LHLT
TBIT
TPPOS
TJCC
TCCS
TSTC
THTC
TPDL
TPLLS
TPDD
CLHT
CHLT
RCOP
RCOH
RCOL
RSRC
RHRC
RPDL
RPLLS
RPDD
Symbol
Symbol
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
LVDS Low-to-High Transition Time, (Figure 2),
PRE = 0.75V (disabled)
LVDS Low-to-High Transition Time, (Figure 2),
PRE = Vcc (max)
LVDS High-to-Low Transition Time, (Figure 2),
PRE = 0.75V (disabled)
LVDS High-to-Low Transition Time, (Figure 2),
PRE = Vcc (max)
Transmitter Bit Width
Transmitter Pulse Positions -
Normalized
Tranmitter Jitter - Cycle-to-Cycle
TxOUT Channel to Channel Skew
TxIN Setup to TxCLK IN, (Figure 5)
TxIN Hold to TxCLK IN, (Figure 5)
Transmitter Propagation Delay - Latency, (Figure 7)
Transmitter Phase Lock Loop Set, (Figure 9)
Transmitter Powerdown Delay, (Figure 11)
CMOS/TTL Low-to-High Transition Time, Rx data out,
(Figure 3)
CMOS/TTL Low-to-High Transition Time, Rx clock
out, (Figure 3)
CMOS/TTL High-to-Low Transition Time, Rx data out,
(Figure 3)
CMOS/TTL High-to-Low Transition Time, Rx clock
out, (Figure 3)
RxCLK OUT Period, (Figure 6)
RxCLK OUT High Time, (Figure 6),
(Note 4)
RxCLK OUT Low Time, (Figure 6),
(Note 4)
RxOUT Setup to RxCLK
OUT,(Figure 6)
RxOUT Hold to RxCLK OUT,
(Figure 6), (Note 4)
Receiver Propagation Delay - Latency, (Figure 8)
Receiver Phase Lock Loop Set, (Figure 10)
Receiver Powerdown Delay, (Figure 12)
Parameter
Parameter
f = 112 MHz
f = 66 MHz
f = 112 MHz
f = 66 MHz
f = 112 MHz
f = 66 MHz
f = 112 MHz
f = 66 MHz
f = 66 MHz,
112MHz
f = 65 to 112
MHz
5
1.5(TCIP)+3.72
3(TCIP)+4.0
− 200
8.928
Min
Min
2.5
3.5
6.0
3.5
6.0
2.4
3.6
3.4
6.0
0
1.5(TCIP)+4.4
3(TCIP)+4.8
1/7 TCIP
0.14
0.11
0.16
0.11
Typ
100
Typ
40
0
T
1.5(TCIP)+6.24
3(TCIP)+6.5
+200
15.38
Max
100
Max
0.7
0.6
0.8
0.7
10
2.0
1.0
2.0
1.0
10
1
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ms
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ns
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µs