NP8P128A13BSM60E Micron Technology Inc, NP8P128A13BSM60E Datasheet - Page 17

• Manufacturer Part Number: NP8P128A13BSM60E
• Manufacturer: Micron Technology Inc

Specifications of NP8P128A13BSM60E

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Numonyx® Omneo™ P8P Datasheet
5.0
Table 6:
Notes:
1.
2.
3.
5.1
5.2
Note:
5.3
5.4
August 2010
316144-07
Read (Main Array)
Read (Status, Query, Identifier)
Output Disable
Standby
Reset
Write
See
X = Don’t care (L or H)
OE# and WE# should never be asserted simultaneously. If done so, OE# overrides WE#.
not be attempted.
Write operations with invalid V
Table 8, “Command Sequences in x16 Bus Mode” on page 20
Bus Operations
State
Bus Operations
CE# at V
assumed to be valid. OE#-low activates the outputs and gates selected data onto the I/
O bus. WE#-low enables device write operations. When the VPP voltage
(lockout voltage), only read operations are enabled.
Reads
To perform a read operation, RST# and WE# must be deasserted while CE# and OE#
are asserted. CE# is the device-select control. When asserted, it enables the flash
memory device. OE# is the data-output control. When asserted, the addressed flash
memory data is driven onto the I/O bus.
Writes
To perform a write operation, both CE# and WE# are asserted while RST# and OE# are
deasserted. During a write operation, address and data are latched on the rising edge
of WE# or CE#, whichever occurs first.
page 19
while
command. See
Output Disable
When OE# is deasserted, device outputs DQ[15:0] are disabled and placed in a high-
impedance (High-Z) state, WAIT is also placed in High-Z.
Standby
When CE# is deasserted the device is deselected and placed in standby, substantially
reducing power consumption. In standby, the data outputs are placed in High-Z,
independent of the level placed on OE#. Standby current, I
measured over any 5 ms time interval, 5 μs after CE# is deasserted. During standby,
average current is measured over the same time interval 5 μs after CE# is deasserted.
Table 8, “Command Sequences in x16 Bus Mode” on page 20
shows the bus cycle sequence for each of the supported device commands,
IL
and RST# at V
Section 16.0, “AC Characteristics” on page 62
RST#
V
V
V
V
V
V
IH
IH
IH
IH
IH
IL
CC
IH
and/or V
enables device read operations. Addresses are always
CE#
V
V
V
V
V
X
IH
IL
IL
IL
IL
PP
voltages can produce spurious results and should
Table 7, “Command Codes and Descriptions” on
OE#
V
V
V
V
X
X
IH
IH
IL
IL
WE#
V
V
V
V
X
X
IH
IH
IH
IL
for valid D
CCS
for signal-timing details.
, is the average current
IN
DQ[15:0]
during a write operation.
High-Z
High-Z
High-Z
describes each
D
D
D
OUT
OUT
IN
≤
VPPLK
Note
2
2
1
17