NP8P128A13BSM60E Micron Technology Inc, NP8P128A13BSM60E Datasheet - Page 25

• Manufacturer Part Number: NP8P128A13BSM60E
• Manufacturer: Micron Technology Inc

Specifications of NP8P128A13BSM60E

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Numonyx® Omneo™ P8P Datasheet
8.2
8.3
August 2010
316144-07
Bit Alterable Word Write Command
The Bit Alterable Word Write Command executes just like Word Program Command
(40h/10h), using a two-write command sequence. The Bit Alterable Write Setup
command (42h) is written to the CUI followed by the specific address and data to be
written. The WSM will start executing the programming algorithm, but the data written
to CUI will be directly overwritten into the PCM memory unlike flash memory, which can
only be written from 1 to 0 without a prior erase of the entire block. See
Alterability vs. Flash Bit-Masking” on page
Bit Masking, which means software cannot use a “1” in a data mask to produce no
change of the memory cell, as might occur with floating gate flash.
Buffered Program Command
A Buffered Program command sequence initiates the loading of a variable number of
words, up to the buffer size (32 words), into the program buffer and after that into the
PCM device. First, the Buffered Program setup command is issued along with the Block
Address
page
word count is given to the part with the Block Address.
On the next write, a device starting address is given along with the Program Buffer
data. Subsequent writes provide additional device addresses and data, depending on
the count. All subsequent addresses must lie within the starting address plus the buffer
size. Maximum programming performance and lower power are obtained by aligning
the starting address at the beginning of a 32 word boundary. A misaligned starting
address is not allowed and will result in invalid data. After the final buffer data is given,
a Program Buffer Confirm command is issued. This initiates the WSM (Write State
Machine) to begin copying the buffer data to the PCM array.
If a command other than Buffered Program Confirm command (D0h) is written to the
device, an “Invalid Command/Sequence” error will be generated and Status Register
bits SR.5 and SR.4 will be set to a “1.” For additional buffer writes, issue another
Program Buffer Setup command and check SR.7. If an error occurs while writing, the
device will stop writing, and Status Register bit SR.4 will be set to a “1” to indicate a
program failure. The internal WSM verify only detects errors for “1”s that do not
successfully program to “0”s.
If a program error is detected, the Status Register should be cleared by the user before
issuing the next program command. Additionally, if the user attempts to program past
the block boundary with a Program Buffer command, the device will abort the Program
Buffer operation. This will generate an “Invalid Command/Sequence” error and Status
Register bits SR.5 and SR.4 will be set to a “1. All bus cycles in the buffered
programming sequence should be addressed to the same block. If a buffered
programming is attempted while the V
be set to “1”.
Buffered write attempts with invalid V
should not be attempted. Buffered program operations with V
produce spurious results and should not be attempted.
Successful programming requires that the addressed block’s locking status to be
cleared. If the block is locked down, then the WP# pin must be raised high and then the
block could be unlocked to execute a program operation. An attempt to program a
locked block results in setting of SR.4 and SR.1 to a ‘1’ (i.e. “Error in Programming”).
75). When Status Register bit 7 is set to 1, the buffer is ready for loading. Now a
(Section 32, “Buffer Program or Bit Alterable Buffer Write Flowchart” on
CC
PP
≤
and V
V
26. This overwrite function eliminates Flash
PPLK
PP
, Status Register bits SR.4 and SR.3 will
voltages produce spurious results and
IH
< RST# < V
Table 12, “Bit
HH
may
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