LM4934WL National Semiconductor, LM4934WL Datasheet - Page 11

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LM4934WL

Manufacturer Part Number
LM4934WL
Description
Manufacturer
National Semiconductor
Datasheet

Specifications of LM4934WL

Lead Free Status / Rohs Status
Supplier Unconfirmed
System Control
The LM4934 is controlled via either a three wire SPI or a two wire I
MODE is cleared the device is in I
operating mode, interfaces, data converters, mixers and amplifiers. The LM4934 is controlled by writing 8 bit data into a series
of write-only registers, the device is always a slave for both type of interfaces.
THREE WIRE, SPI INTERFACE (MODE = 1)
When the part is configured as an SPI device and the enable (ENB) line is lowered the serial data on SDI is clocked in on the
rising edge of the SCK line. The protocol used is 16bit, MSB first. The upper 8 bits (15:8) are used to select an address within
the device, the lower 8 bits (7:0) contain the updated data for this register.
TWO WIRE I
2
C COMPATIBLE INTERFACE (MODE = 0)
2
C mode, when MODE is set the device is in SPI mode. This interface is used to configure the
Three Wire Mode Write Bus Transaction
FIGURE 3. Three Wire Mode Write Bus
Two Wire Mode Write Bus Transaction
FIGURE 4. Two Wire Mode Write Bus
Three Wire Mode Write Bus Timing
Two Wire Mode Write Bus Timing
11
2
C compatible interface, selectable with the MODE pin. When
20166962
201669J6
20166960
20166959
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