LM4934WL National Semiconductor, LM4934WL Datasheet - Page 18

• Manufacturer Part Number: LM4934WL
• Manufacturer: National Semiconductor

Specifications of LM4934WL

• Lead Free Status / Rohs Status: Supplier Unconfirmed

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System Controls
PLL Configuration Registers
PLL M DIVIDER CONFIGURATION REGISTER
This register is used to control the input divider of the PLL.
PLL_M (0Ah) (Set = logic 1, Clear = logic 0)
NOTES:
The M divider should be set such that the output of the divider is between 0.5 and 5MHz. See the PLL setup section for details.
The divider of the M divider is derived from PLL_M as such:
M = (PLL_M+1) / 2
MONO_IN_GAIN_2
ANA_R_GAIN_2
ANA_L_GAIN_2
Bits
6:0
DIG_R_GAIN_1
0
0
0
0
1
1
1
1
DIG_L_GAIN_1
0
0
1
1
(Continued)
Register
PLL_M
MONO_IN_GAIN_1
TABLE 12. Analog Input Amplifier Gain Select
ANA_R_GAIN_1
ANA_L_GAIN_1
0
0
1
1
0
0
1
1
TABLE 13. DAC Gain Select
Description
Programs the PLL input divider to select:
DIG_R_GAIN_1
DIG_L_GAIN_1
18
PLL_M
126
127
...
0
1
2
3
4
0
1
0
1
MONO_IN_GAIN_0
ANA_R_GAIN_0
ANA_L_GAIN_0
0
1
0
1
0
1
0
1
Divide Ratio
Input Gain Setting
Divider Off
Input Gain Setting
63.5
3 →
1.5
2.5
64
1
2
–3dB
0dB
3dB
6dB
–6dB
–3dB
12dB
15dB
0dB
3dB
6dB
9dB