LM4934WL National Semiconductor, LM4934WL Datasheet - Page 20

• Manufacturer Part Number: LM4934WL
• Manufacturer: National Semiconductor

Specifications of LM4934WL

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PLL Configuration Registers
PLL N MODULATOR AND DITHER SELECT CONFIGURATION REGISTER
This register is used to control the Fractional component of the PLL.
PLL_N_MOD (0Ch) (Set = logic 1, Clear = logic 0)
NOTES:
The complete N divider is a fractional divider as such:
N = PLL_N + (PLL_N_MOD/32)
If the modulus input is zero, then the N divider is simply an integer N divider. The output from the PLL is determined by the following formula:
Fout = (Fin * N) / (M * P)
Please see over for more details on the PLL and common settings.
Bits
4:0
6:5
7
DITHER_LEVEL
PLL_N_MOD
FAST_VCO
Register
(Continued)
DITHER_LEVEL
If set the VCO maximum and minimum frequencies are raised:
PLL_N_MOD
FAST_VCO
This programs the PLL N Modulator’s fractional component:
2 → 30
Allows control over the dither used by the N Modulator
31
00
01
10
11
0
1
0
1
20
Description
DAC Sub-system Input Source
Fractional Addition
Maximum F
2/32 → 30/32
Medium (32)
40–55MHz
55–80MHz
Small (16)
Large (48)
31/32
0/32
1/32
Off
VCO